Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies

A new LDPC decoder hardware implementation with improved error rates

Philipp Schläfer, Stefan Scholl, E. Leonardi, Norbert Wehn

Published Nov 1, 2015• 5 citations
Publisher

Abstract

LDPC codes are commonly decoded by conventional belief propagation algorithms like the min-sum algorithm. However especially for small block lengths belief propagation performs poorly in comparison to maximum likelihood decoding. In this paper we propose a new decoding algorithm, that is inspired by augmented belief propagation from literature and present hardware architectures and implementations for 28nm ASIC technology. The new decoder has a much higher complexity, but provides a gain of up to 1.2 dB signal-to-noise ratio compared to conventional belief propagation decoding.

DOI
10.1109/aeect.2015.7360541

Related papers

Saturated Min-Sum Decoding: An “Afterburner” for LDPC Decoder Hardware

Stefan Scholl, Philipp Schläfer, Norbert Wehn

LDPC codes are usually decoded by iterative belief propagation. However especially for small block lengths conventional belief propagation exhibits significant losses in signal-to-noise ratio compared to maximum likelihood decoding. In this paper we propose the combination of a conventional min-sum decoder enhanced by an advanced decoding scheme, that acts as a kind of “afterburner” to improve the frame error rate. We present hardware architectures and implementation results for a 28nm ASIC technology. The new decoder has a slightly higher complexity, but provides a gain of up to 1.6 dB signal-to-noise ratio over conventional belief propagation decoding for short block length. In addition, we show, that the new decoder implementation can decrease the amount of dark silicon.

Design, Automation, and Test in Europe•Jan 1, 2016•14 citations

Improved LDPC decoding algorithms based on min-sum algorithm

Y.V. A. C. Kumara, Chandika Bandara Wavegedara

Low-Density Parity check (LDPC) codes offer high-performance error correction near the Shannon limit which employs large code lengths and some iterations in the decoding process. The conventional decoding algorithm of LDPC is the Log Likelihood Ratio based Belief Propagation (LLR BP) which is also known as the `Sum-Product algorithm' which gives the best decoding performance and requires the most computational complexity and implementations with increased hardware complexity. Another simpler variant of this algorithm is used which is known as `min-sum algorithm' which reduces computational complexity as well as hardware complexity but with reduced accuracy. This paper analyzes the reason min-sum algorithm is more prone to errors when compared to the sum-product algorithm, and puts forward two improved algorithms which improve the performance of the min-sum algorithm with comparable algorithmic complexity.

Moratuwa Engineering Research Conference (MERCon)•Apr 1, 2016•8 citations

Belief-propagation with information correction: improved near maximum-likelihood decoding of low-density parity-check codes

Nedeljko Varnica, M.P.C. Fossorier

We propose an improved belief-propagation (BP) decoder for low-density parity-check (LDPC) codes based on channel information correction. We show that our algorithm achieves sizeable performance gains (in waterfall and error floor regions) compared to the standard BP decoder. We verify by examples that the proposed decoder almost achieves the maximum-likelihood decoding performance for short LDPC codes

IEEE International Symposium on Information Theory (ISIT)•Dec 23, 2004•18 citations

Hardware Implementation of LDPC Decoders

Christian Spagnol, Emanuel Mihai Popovici, William Peter Marnane

Low density parity check (LDPC) codes over are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over codes. This paper proposes a novel variation of the belief propagation algorithm for LDPC codes. The new algorithm results in a reduced hardware complexity when imple- mented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over decoder is feasible for short to medium length codes. The additional com- plexity of the decoder is balanced by the superior performance of LDPC codes.

•Jan 1, 2009•6 citations

Augmented decoders for LDPC codes

Alex Rigby, JC Olivier, Hermanus Carel Myburgh +2 more

The performance of a belief propagation decoder for low-density parity-check codes is limited by the presence of trapping sets in the code’s graph. This leads to an error floor at higher signal-to-noise ratios. We propose the use of an augmented decoder which operates by iteratively decoding on a set of graphs which have a subset of repeated check nodes. We compare the augmented decoder to other modified belief propagation decoders that have been presented in the literature. We show that for all the codes considered, the augmented decoder yields the best frame error rate in the error floor region.

EURASIP Journal on Wireless Communications and Networking•Aug 2, 2018•3 citations

On Implementation of Min-Sum Algorithm and Its Modifications for Decoding Low-Density Parity-Check (LDPC) Codes

J. Zhao, Farhad Zarkeshvari, Amir H. Banihashemi

The effects of clipping and quantization on the performance of the min-sum algorithm for the decoding of low-density parity-check (LDPC) codes at short and intermediate block lengths are studied. It is shown that in many cases, only four quantization bits suffice to obtain close to ideal performance over a wide range of signal-to-noise ratios. Moreover, we propose modifications to the min-sum algorithm that improve the performance by a few tenths of a decibel with just a small increase in decoding complexity. A quantized version of these modified algorithms is also studied. It is shown that, when optimized, modified quantized min-sum algorithms perform very close to, and in some cases even slightly outperform, the ideal belief-propagation algorithm at observed error rates.

IEEE Transactions on Communications•Apr 1, 2005•283 citations
LDPC codes are commonly decoded by conventional belief propagation algorithms like the min-sum algorithm. However especially for small block lengths belief propagation performs poorly in comparison to maximum likelihood decoding. In this paper we propose a new decoding algorithm, that is inspired by augmented belief propagation from literature and present hardware architectures and implementations for 28nm ASIC technology. The new decoder has a much higher complexity, but provides a gain of up to 1.2 dB signal-to-noise ratio compared to conventional belief propagation decoding.
LDPC codes are usually decoded by iterative belief propagation. However especially for small block lengths conventional belief propagation exhibits significant losses in signal-to-noise ratio compared to maximum likelihood decoding. In this paper we propose the combination of a conventional min-sum decoder enhanced by an advanced decoding scheme, that acts as a kind of “afterburner” to improve the frame error rate. We present hardware architectures and implementation results for a 28nm ASIC technology. The new decoder has a slightly higher complexity, but provides a gain of up to 1.6 dB signal-to-noise ratio over conventional belief propagation decoding for short block length. In addition, we show, that the new decoder implementation can decrease the amount of dark silicon.
Low-Density Parity check (LDPC) codes offer high-performance error correction near the Shannon limit which employs large code lengths and some iterations in the decoding process. The conventional decoding algorithm of LDPC is the Log Likelihood Ratio based Belief Propagation (LLR BP) which is also known as the `Sum-Product algorithm' which gives the best decoding performance and requires the most computational complexity and implementations with increased hardware complexity. Another simpler variant of this algorithm is used which is known as `min-sum algorithm' which reduces computational complexity as well as hardware complexity but with reduced accuracy. This paper analyzes the reason min-sum algorithm is more prone to errors when compared to the sum-product algorithm, and puts forward two improved algorithms which improve the performance of the min-sum algorithm with comparable algorithmic complexity.
Low density parity check (LDPC) codes over are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over codes. This paper proposes a novel variation of the belief propagation algorithm for LDPC codes. The new algorithm results in a reduced hardware complexity when imple- mented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over decoder is feasible for short to medium length codes. The additional com- plexity of the decoder is balanced by the superior performance of LDPC codes.
The performance of a belief propagation decoder for low-density parity-check codes is limited by the presence of trapping sets in the code’s graph. This leads to an error floor at higher signal-to-noise ratios. We propose the use of an augmented decoder which operates by iteratively decoding on a set of graphs which have a subset of repeated check nodes. We compare the augmented decoder to other modified belief propagation decoders that have been presented in the literature. We show that for all the codes considered, the augmented decoder yields the best frame error rate in the error floor region.
The effects of clipping and quantization on the performance of the min-sum algorithm for the decoding of low-density parity-check (LDPC) codes at short and intermediate block lengths are studied. It is shown that in many cases, only four quantization bits suffice to obtain close to ideal performance over a wide range of signal-to-noise ratios. Moreover, we propose modifications to the min-sum algorithm that improve the performance by a few tenths of a decibel with just a small increase in decoding complexity. A quantized version of these modified algorithms is also studied. It is shown that, when optimized, modified quantized min-sum algorithms perform very close to, and in some cases even slightly outperform, the ideal belief-propagation algorithm at observed error rates.