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A Bit-Serial Approximate Min-SumLDPCDecoder and FPGAImplementation

Anthony ChanCarusone

Published Jan 1, 2006• 0 citations
OpenAlex

Abstract

Wepropose abit-serial LDPCdecoding scheme toreduceA.LDPCcodes andmin-sum decoding interconnect complexity infully-parallel low-density parity-check de- A binary (NN -M) LDPCcode, C,isthenull space ofasparse coders. Bit-serial decoding alsofacilitates efficient implementation of M N wordlength-programmable LDPCdecoding whichisessential forgear M xN parity-check matrix, H.Itcanalso bedescribed byabipartite shift decoding. Tosimplify theimplementation ofbit-serial decodinggraph, orTannergraph. Tannergraph ofanLDPC codeconsists of wepropose anewapproximation tothecheck update function inthe twosetofnodes. Checknodes{Cl, C2,...,CM}represent therows min-sum decoding algorithm. Thenewcheck update rule computes onlyofH andvariable nodes{VI V2,*.* VN}represent thecolumns. An theabsolute minimumandapplies acorrection tooutgoing messages if ' ' t required. Wepresent a650-Mbps bit-serial (480, 355)RS-based LDPC edgeconnects thechecknodecmtothevariable nodevnifandonly decoder implemented onasingle Altera Stratix EP1S80 FPGAdevice. To ifHmn isnonzero. Foracodewithafull-rank M xN parity-check ourknowledge, this isthefastest FPGA-based LDPCdecoder reported matrix, H,thecoderate isR = - M/N.We denote thesetof intheliterature. variables thatparticipate incheckCm asN(m) = {n:Hmn= 1}andthesetofchecks inwhichthevariable vnparticipates as

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Wepropose abit-serial LDPCdecoding scheme toreduceA.LDPCcodes andmin-sum decoding interconnect complexity infully-parallel low-density parity-check de- A binary (NN -M) LDPCcode, C,isthenull space ofasparse coders. Bit-serial decoding alsofacilitates efficient implementation of M N wordlength-programmable LDPCdecoding whichisessential forgear M xN parity-check matrix, H.Itcanalso bedescribed byabipartite shift decoding. Tosimplify theimplementation ofbit-serial decodinggraph, orTannergraph. Tannergraph ofanLDPC codeconsists of wepropose anewapproximation tothecheck update function inthe twosetofnodes. Checknodes{Cl, C2,...,CM}represent therows min-sum decoding algorithm. Thenewcheck update rule computes onlyofH andvariable nodes{VI V2,. VN}represent thecolumns. An theabsolute minimumandapplies acorrection tooutgoing messages if ' ' t required. Wepresent a650-Mbps bit-serial (480, 355)RS-based LDPC edgeconnects thechecknodecmtothevariable nodevnifandonly decoder implemented onasingle Altera Stratix EP1S80 FPGAdevice. To ifHmn isnonzero. Foracodewithafull-rank M xN parity-check ourknowledge, this isthefastest FPGA-based LDPCdecoder reported matrix, H,thecoderate isR = - M/N.We denote thesetof intheliterature. variables thatparticipate incheckCm asN(m) = {n:Hmn= 1}andthesetofchecks inwhichthevariable vnparticipates as
This paper addresses binary message-passing (MP) decoding for nonbinary low-density parity-check (NB-LDPC) codes based on the binary image of Galois field symbols. The parity-check matrix of NB-LDPC codes in binary form is used to perform MP. The corresponding nonbinary check node (CN) update and variable node (VN) update can thus be decomposed to a set of binary sub-CN updates and sub-VN updates with much lower computational complexity. In particular, we start from adapting the binary parity-check matrix with Gaussian elimination. Then, we add redundant rows to the parity-check matrix instead of adaptation to further improve the performance. A min-max operation based on the expanded matrix is proposed for the CN update. It not only decreases the computational complexity incurred by Gaussian elimination but also improves the error performance. Simulation results show that the bit-level decoding with min-max operation can achieve similar error performance as the extended min-sum algorithm, but the computational complexity can be lower than the min-sum algorithm for binary LDPC codes.
This thesis is focused on the design and implementation of binary low-density parity-check (LDPC) code decoders for high-speed modern communication systems. The basic of LDPC codes and the performance and bottlenecks, in terms of complexity and hardware efficiency, of the main soft-decision and hard-decision decoding algorithms (such as Min-Sum, Optimized 2-bit Min-Sum and Reliability-based iterative Majority-Logic) are analyzed. The complexity and performance of those algorithms are improved to allow efficient hardware architectures.\n\nA new decoding algorithm called One-Minimum Min-Sum is proposed. It reduces considerably the complexity of the check node update equations of the Min-Sum algorithm. The second minimum is estimated from the first minimum value by a means of a linear approximation that allows a dynamic adjustment. The Optimized 2-bit Min-Sum algorithm is modified to initialize it with the complete LLR values and to introduce the extrinsic information in the messages sent from the variable nodes. Its variable node equation is reformulated to reduce its complexity. Both algorithms were tested for the (2048,1723) RS-based LDPC code and (16129,15372) LDPC code using an FPGA-based hardware emulator. They exhibit BER performance very close to Min-Sum algorithm and do not introduce early error-floor. \n\nIn order to show the hardware advantages of the proposed algorithms, hardware decoders were implemented in a 90 nm CMOS process and FPGA devices based on two types of architectures: full-parallel and partial-parallel one with horizontal layered schedule. The results show that the decoders are more area-time efficient than other published decoders and that the low-complexity of the Modified Optimized 2-bit Min-Sum allows the implementation of 10 Gbps decoders in current FPGA devices. \n\nFinally, a new hard-decision decoding algorithm, the Historical-Extrinsic Reliability-Based Iterative Decoder, is presented. This algorithm introduces the new idea of considering hard-decision votes as soft-decision to compute the extrinsic information of previous iterations. It is suitable for high-rate codes and improves the BER performance of the previous RBI-MLGD algorithms, with similar complexity.
改进低密度的同等值检查(LDPC ) 译码编码的 min 和的表演的问题在这份报纸被考虑。把算法基于 min 和，为 LDPC 代码译码算法的新奇修改 min 和被建议。如果他们的符号是不同的，建议算法由平均新消息和以前的消息在重复进程修改可变节点消息。与标准 min 和算法相比，修正随仅仅复杂性的小增加被完成，但是显著地改善为常规、不规则的 LDPC 代码译码性能。模拟结果证明我们译码算法修改的性能离为中等长度 LDPC 代码的标准和产品算法的很靠近。
To reduce the complexity of encoder-decoder,the construction of QuasiCyclic Low-Density Parity-Check(QC-LDPC) codes was studied.A simplified method to find the systematic generator matrix from its parity check matrix was introduced which could greatly reduce the encoding complexity and realize linear encode-able codes.A modified Turbo serial message passing schedule for min-sum algorithm was applied with approximately the same performance as the sum-product algorithm,which updated messages immediately and converges fast.Based on the fixed point DSP,a high performance encoder-decoder were designed.The simulation result shows that this algorithm realizes efficient encoding and decoding with low complexity.