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China Communications

Two bit-serial architectures for check node update in min-sum decoding of LDPC codes

HU Qing, He Xuan, Lisha Luo, Kui Cai, Tang Xiaohu

Published Mar 1, 2026• 1 citation
Publisher
DOI
10.23919/jcc.fa.2024-0690.202603

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One of the most important units of Low-Density Parity-Check (LDPC) decoders is the Check-Node Unit.Its main task is to find the first two minimum values among incoming variable-to-check messages and return check-tovariable messages.This block significantly affects the decoding performance, as well as the hardware implementation complexity.In this paper, we first propose a modification to the check-node update rule by introducing two optimal offset factors applied to the check-to-variable messages.Then, we present the Check-Node Unit hardware architecture which performs the proposed algorithm.The main objective of this work aims to improve further the decoding performance for 5 th Generation (5G) LDPC codes.The simulation results show that the proposed algorithm achieves essential improvements in terms of error correction performance.More precisely, the error-floor does not appear within Bit-Error-Rate (BER) of 10 -8 , while the decoding gain increases up to 0.21 dB compared to the baseline Normalized Min-Sum, as well as several state-ofthe-art LDPC-based Min-Sum decoders.
This paper has presented various min-sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. The m-to-2m decoder has been introduced to generate more efficient new hardware implementations of check node update, which can obviously reduce the number of multiplication operations for normalized min-sum algorithm for high rate LDPC codes. Simulations have claimed the performance of normalized min-sum is nearly the same as that of Log-BP, namely the optimal algorithm. In general, this paper has proved that normalized min-sum is good choices as LDPC decoding methods.
In the recent literature, turbo decoding message passing (TDMP) or layered decoding has been proposed for the decoding of low-density parity-check (LDPC) codes using a trellis-based BCJR algorithm in check node units (CNU). We present a new architecture for supporting rate compatible array LDPC codes that uses an offset-based min-sum decoding algorithm instead of the BCJR. The proposed architecture utilizes the value-reuse properties of min-sum and block-serial scheduling of computations, along with TDMP. This novel architecture has the following features: removal of memory needed to store the sum of the variable node messages and the channel values, removal of memory needed to store the variable node messages, 40%-72% savings in storage of extrinsic messages depending on rate of the codes, reduction of routers by 50%, and increase of throughput up to 2times. Implementations on our test-bed FPGA achieve decoded throughputs up to 1.36 Gbps and 2.27 Gbps for each iteration for (5,k) and (3,k) array LDPC codes, respectively. ASIC implementation achieve decoded throughputs up to 5.9 Gbps for each iteration for (5,k) array LDPC codes.