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Wireless Telecommunications Symposium

Fast Parallel Weighted Bit Flipping decoding algorithm for LDPC codes

M. Vanek, Peter Farkaš

Published May 1, 2009• 2 citations
Publisher

Abstract

In this paper a fast version of the parallel weighted bit flipping LDPC decoding algorithm (PWBF) is presented. The idea, which allowed decreasing the computational complexity of the PWBF method, is based on the observation that in dependency on signal to noise ratio, many of the received bits in the codeword of LDPC code could be without error. The augmented algorithm makes tests based on syndromes and symbol involvement in parity checks, which are given by the factor graph corresponding to the chosen LDPC code in order to define so called guaranteed bits. These guaranteed bits do not participate in the decoding calculations further. Simulation results are presented, which show that there is not visible any significant performance deterioration by application of this method and that the approximate speed up of the decoding for the tested codes is about 25% on the selected hardware in comparison with the known PWBF.

DOI
10.1109/wts.2009.5068982

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In this paper a fast version of the parallel weighted bit flipping LDPC decoding algorithm (PWBF) is presented. The idea, which allowed decreasing the computational complexity of the PWBF method, is based on the observation that in dependency on signal to noise ratio, many of the received bits in the codeword of LDPC code could be without error. The augmented algorithm makes tests based on syndromes and symbol involvement in parity checks, which are given by the factor graph corresponding to the chosen LDPC code in order to define so called guaranteed bits. These guaranteed bits do not participate in the decoding calculations further. Simulation results are presented, which show that there is not visible any significant performance deterioration by application of this method and that the approximate speed up of the decoding for the tested codes is about 25% on the selected hardware in comparison with the known PWBF.
In this paper, a weighted multiple bit flipping (WMBF) algorithman for decoding low-density parity-check (LDPC) codes is proposed first. Then the improved WMBF algorithm which we call the efficient weighted bit-flipping (EWBF) algorithm is developed. The EWBF algorithm can dynamically choose either multiple bit-flipping or single bit-flipping in each iteration according to the log-likelihood ratio of the error probability of the received bits. Thus, it can efficiently increase the convergence speed of decoding and prevent the decoding process from falling into loop traps. Compared with the parallel weighted bit-flipping (PWBF) algorithm, the EWBF algorithm can achieve significantly lower computational complexity without performance degradation when the Euclidean geometry (EG)-LDPC codes are decoded. Furthermore, the flipping criterion does not require any parameter adjustment.
Aiming at seeking a low-complexity decoder with fast decoding convergence speed for short or medium low-density parity-check (LDPC) codes, an improved parallel weighted bit-flipping (IPWBF) algorithm, which is applied flexibly for two classes of codes is presented here. For LDPC codes with low column weight in their parity check matrix, both bootstrapping and loop detection procedures, described in the existing literature, are included in IPWBF. Furthermore, a novel delay-handling procedure is introduced to prevent the codeword bits of high reliability from being flipped too hastily. For large column weight finite geometry LDPC codes, only the delay-handling procedure is included in IPWBF to show its effectiveness. Extensive simulation results demonstrate that the proposed algorithm achieves a good tradeoff between performance and complexity.
In order to improve the decoding speed of low density parity check code( LDPC) codes,a fast weighted bit flipping algorithm with partially parallel bit-chosen is proposed. In this scheme,all bits are firstly divided into several blocks according to the stochastic error distribution in the received vector. And then one bit is chosen from each block to form the candidate set of flipped bits. Finally,a proper number of bits are chosen from the candidate set and flipped to implement the decoding. Furthermore,the tree sorting and data pool methods are adopted to decrease the computational complexity of the key module of the proposed algorithm. Compared with the multi-bit flippin( MBF) algorithm by simulations,the proposed scheme and the method of hardware implement can achieve significant improvement in the decoding speed.
Parallel Weighted Bit Flipping(PWBF)can achieve a good decoding performance.However,it is hard for the hardware design and implementation because of the high complexity of its bit-chosen mechanism.By improving the bit-chosen mechanism in PWBF,a low-complexity decoding algorithm is proposed in this paper.Especially,in each iteration step of decoding,after the metric value of every bit is updated,several bits with the largest metric values are flipped.Furthermore,the optimized circuits with low complexity are provided for the critical modules of the proposed algorithm.Compared with the PWBF algorithm,the complexity of LDPC decoders is greatly decreased by use of the proposed algorithm and the optimized circuits.
Because of the speed limitation of the conventional bit-selection strategy in the existing weighted bit flipping algorithms, a high-speed Low-Density Parity-Check (LDPC) decoder cannot be realised. To solve this problem, we propose a fast weighted bit flipping algorithm. Specifically, based on the identically distributed error bits, a parallel bit-selection method is proposed to reduce the selection delay of the flipped bits. The delay analysis demonstrates that, the decoding speed of LDPC codes can be significantly improved by the proposed algorithm. Furthermore, simulation results verify the validity of the proposed algorithm.