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China Communications

Fast weighted bit flipping algorithm for higher-speed decoding of Low-Density Parity-Check codes

Kexiang Ma, Yongzhao Li, Hailin Zhang

Published Sep 1, 2013• 6 citations
Publisher

Abstract

Because of the speed limitation of the conventional bit-selection strategy in the existing weighted bit flipping algorithms, a high-speed Low-Density Parity-Check (LDPC) decoder cannot be realised. To solve this problem, we propose a fast weighted bit flipping algorithm. Specifically, based on the identically distributed error bits, a parallel bit-selection method is proposed to reduce the selection delay of the flipped bits. The delay analysis demonstrates that, the decoding speed of LDPC codes can be significantly improved by the proposed algorithm. Furthermore, simulation results verify the validity of the proposed algorithm.

DOI
10.1109/cc.2013.6623509

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Because of the speed limitation of the conventional bit-selection strategy in the existing weighted bit flipping algorithms, a high-speed Low-Density Parity-Check (LDPC) decoder cannot be realised. To solve this problem, we propose a fast weighted bit flipping algorithm. Specifically, based on the identically distributed error bits, a parallel bit-selection method is proposed to reduce the selection delay of the flipped bits. The delay analysis demonstrates that, the decoding speed of LDPC codes can be significantly improved by the proposed algorithm. Furthermore, simulation results verify the validity of the proposed algorithm.
Due to the speed limitation of the conventional bit-chosen strategy in the existing weighted bit flipping algorithms, a high-speed LDPC decoder cannot be realized. To solve this problem, we propose a fast weighted bit flipping (FWBF) algorithm. Specifically, based on the stochastic error bitmap of the received vector, a partially parallel bit-choose strategy is adopted to lower the delay of choosing the bit flipped. Because of its partially parallel structure, the novel strategy can be well incorporated into the LDPC decoder [1]. The analysis of the decoding delay demonstrates that, the decoding speed can be greatly improved by adopting the proposed FWBF algorithm. Further, simulation results verify the validity of the proposed algorithm.
Aiming at seeking a low-complexity decoder with fast decoding convergence speed for short or medium low-density parity-check (LDPC) codes, an improved parallel weighted bit-flipping (IPWBF) algorithm, which is applied flexibly for two classes of codes is presented here. For LDPC codes with low column weight in their parity check matrix, both bootstrapping and loop detection procedures, described in the existing literature, are included in IPWBF. Furthermore, a novel delay-handling procedure is introduced to prevent the codeword bits of high reliability from being flipped too hastily. For large column weight finite geometry LDPC codes, only the delay-handling procedure is included in IPWBF to show its effectiveness. Extensive simulation results demonstrate that the proposed algorithm achieves a good tradeoff between performance and complexity.
In order to improve the decoding speed of low density parity check code( LDPC) codes,a fast weighted bit flipping algorithm with partially parallel bit-chosen is proposed. In this scheme,all bits are firstly divided into several blocks according to the stochastic error distribution in the received vector. And then one bit is chosen from each block to form the candidate set of flipped bits. Finally,a proper number of bits are chosen from the candidate set and flipped to implement the decoding. Furthermore,the tree sorting and data pool methods are adopted to decrease the computational complexity of the key module of the proposed algorithm. Compared with the multi-bit flippin( MBF) algorithm by simulations,the proposed scheme and the method of hardware implement can achieve significant improvement in the decoding speed.
In this paper a fast version of the parallel weighted bit flipping LDPC decoding algorithm (PWBF) is presented. The idea, which allowed decreasing the computational complexity of the PWBF method, is based on the observation that in dependency on signal to noise ratio, many of the received bits in the codeword of LDPC code could be without error. The augmented algorithm makes tests based on syndromes and symbol involvement in parity checks, which are given by the factor graph corresponding to the chosen LDPC code in order to define so called guaranteed bits. These guaranteed bits do not participate in the decoding calculations further. Simulation results are presented, which show that there is not visible any significant performance deterioration by application of this method and that the approximate speed up of the decoding for the tested codes is about 25% on the selected hardware in comparison with the known PWBF.
In weighted bit-flipping-based algorithms for low-density parity-check (LDPC) codes, due to the existence of overconfident incorrectly received bits, the metric values of the corresponding bits will always be wrong in the decoding process. Since these bits cannot be flipped, decoding failure results. To solve this problem, an improved parallel weighted bit flipping algorithm is proposed. Specifically, a reliability-saturation strategy is adopted to increase the flipping probability of the overconfident incorrectly received bits. Simulation results show that the error floor of LDPC codes is greatly lowered.
In order to improve the bit-flipping (BF) decoding algorithms, a weighted hard-decision based BF decoding algorithm for low-density parity-check (LDPC) codes is presented, in which the weights of variable-nodes are employed. A new metric is defined for the weight of candidate bits not only in unsatisfied parity check equations but also in satisfied ones. The connection between min-sum decoding algorithm and the proposed algorithm is presented. Simulation results show that the new decoding algorithm can provide better FER performance and faster convergence speed than the original candidate bit based bit-flipping (CBBF) algorithm.