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IEEE Transactions on Applied Superconductivity

Functional modeling of RSFQ circuits using Verilog HDL

Kris Gaj, Chin-Hong Cheah, Eby G. Friedman, M. J. Feldman

Published Jun 1, 1997• 38 citations
Publisher

Abstract

Circuit level simulation is too slow to be used for verification of function and timing of large RSFQ circuits. The alternative, known from semiconductor digital circuit design, is simulating at the logic (gate) instead of the circuit (transistor or junction) level. Using a hardware description language (HDL) such as Verilog, it is possible to write functional model of each of the RSFQ basic gates. A large RSFQ circuit composed of hundreds gates and thousands Josephson junctions can then be simulated using standard semiconductor industry CAD tools. We have developed a library of Verilog models for over 15 basic RSFQ gates. We describe in detail our model for the DRO RSFQ cell. We show how this model can be generalized for other more complex cells. Our library has been verified by employing it in the design of timing for three large RSFQ circuits.

DOI
10.1109/77.622000

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Circuit level simulation is too slow to be used for verification of function and timing of large RSFQ circuits. The alternative, known from semiconductor digital circuit design, is simulating at the logic (gate) instead of the circuit (transistor or junction) level. Using a hardware description language (HDL) such as Verilog, it is possible to write functional model of each of the RSFQ basic gates. A large RSFQ circuit composed of hundreds gates and thousands Josephson junctions can then be simulated using standard semiconductor industry CAD tools. We have developed a library of Verilog models for over 15 basic RSFQ gates. We describe in detail our model for the DRO RSFQ cell. We show how this model can be generalized for other more complex cells. Our library has been verified by employing it in the design of timing for three large RSFQ circuits.
We have proposed a cell-based design approach for rapid single flux quantum (RSFQ) logic circuits. In our design approach, a binary decision diagram (BDD) is used for representation of logical functions in order to reduce the number of gates. We have made a standard cell library, which is composed of only five basic cells. We add one-junction Josephson transmission line (JTL) to the edge of the input and the output node of some basic cells, by which no deterioration of the DC bias margin is observed for the connection of each cell. In the layout level, the size and the position of the input/output node of each cell are equalized. The standard cell circuits were fabricated by NEC 2.5 kA/cm/sup 2/ and Hypres 1.0 kA/cm/sup 2/ Nb standard process and they were tested at low speed.
Exascale computing and its associated increasingly massive amounts of data require increasingly efficient computing platforms; and semiconductor technology is struggling to keep up. Meanwhile, superconducting electronics (SCE) is increasingly gaining interest in both industry and academia as a serious contender to replace silicon for supercomputing. In particular, nonresistively biased single-flux quantum (SFQ) circuits have a theoretical potential of three orders of magnitude reduction in power accompanied with one order of magnitude of higher speed, and adiabatic quantum-flux-parametron (AQFP) circuits possess a theoretical potential of six orders of magnitude reduction in power when compared to the state-of-the-art semiconductor circuits. Unfortunately, the SCE community lacks a reliable design flow. Rather than creating a complete design flow from scratch, it is often more efficient to reuse well-established semiconductor tool flows developed by EDA companies that have benefited from research and development over the past half-century. One of the components of this flow is the hardware description language (HDL) modeling of gates for behavioral and functional simulation of large netlists. The previous HDL models proposed for SCE lack modularity are not compatible with existing CMOS standards, and are overly complex. This article presents SystemVerilog models for SFQ and AQFP gates and the circuits that interface between them. Our models are compatible with standard delay format and commercial simulators. They offer a generalizable modular debugging platform, are elegant and conceptual, and can capture many circuit parameters, environmental effects, and advanced SCE phenomena.
Rapid single flux quantum (RSFQ) digital circuits have reached the level of medium- to large-scale of integration. At this level, existing design methodologies, developed specifically for RSFQ circuits, have become computationally inefficient. Applying mature semiconductor methodologies to the design of RSFQ circuits, one encounters substantial difficulties originating from the differences between both technologies. In this paper, a new design methodology aimed at large-scale RSFQ circuits is proposed. This methodology is based on a semiconductor semicustom design approach. An established design methodology for small-stale RSFQ digital circuits, based on circuit (junction-level) simulation and device parameter optimization, is used for the design of basic RSFQ cells. A library composed of about 20 basic RSFQ cells has been developed based on this approach. A novel design methodology for large-scale circuits, presented in this paper, is based on logic (gate-level) simulation and timing optimization. This methodology has been implemented around the Cadence integrated design environment and used successfully at the University of Rochester for the design of two large-scale digital circuits.
Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.
The quantum algorithms could efficiently solve problems having exponential classical solutions [8]. The circuit model is considered as the most feasible implementation of the quantum algorithms [17]. This paper tries to find common ground between classical circuit design techniques and quantum computation, by identifying quantum circuit specification and simulation tools under the form of Hardware Description Languages (HDLs). The HDL-based simulation approach could reduce the complexity of quantum circuit simulation, by considering entanglement as the main source of gate-level simulation complexity, and isolating it in an automated manner. This is possible by taking advantage of the HDL feature of describing a circuit with both structural and functional architectures. We also performed an analysis of our methodology effectiveness, for the arithmetic circuits involved in Shor's algorithm and the circuits implementing Grover's algorithm. Our method is further improved by an entangled representation avoidance technique called 'bubble logic insertion'.
Work is in progress throughout the globe to efficiently use the potential of the quantum theory of computation over their classical counterpart and hence there is a need of building quantum computing hardware. The target of building quantum computers can be achieved if we have better tools for the design of quantum hardware. Quantum circuit simulators are tools for the logic verification of quantum circuits and they can be an essential component of quantum CAD tools in the future. This work is the extension of the previous work by the authors, in order to increase the efficiency of the simulator and to incorporate more components in the gate library. In this paper we have proposed an efficient simulator which can simulate a quantum circuit specified using the proposed quantum hardware descriptive language (QHDL).