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IEEE Transactions on Applied Superconductivity

A High-Throughput Single-Flux Quantum Floating-Point Serial Divider Using the Signed-Digit Representation

Masamitsu Tanaka, Koji Obata, Kazumasa Takagi, Naofumi Takagi, Akira Fujimaki, Nobuyuki Yoshikawa

Published May 27, 2009• 6 citations
Publisher

Abstract

We propose a floating-point serial divider for a single-flux quantum (SFQ) logic implementation based on a hardware algorithm of division using subtract and shift operations. Fast serial calculations are performed by utilizing the signed-digit representation. The divider is implemented with a regularly aligned pipeline structure called a systolic array. The processing element of the systolic array is designed using several logic gates unique to the SFQ circuits, to reduce the number of pipeline stages. As a result, high throughput and low latency is achieved with a small circuit size. The throughput approaches the maximum throughput of serial processing. A 4-bit divider was fabricated using the 2.5-kA/cm2niobium process technology, and successful operation up to 19 GHz was demonstrated.

DOI
10.1109/tasc.2009.2018537

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We propose a floating-point serial divider for a single-flux quantum (SFQ) logic implementation based on a hardware algorithm of division using subtract and shift operations. Fast serial calculations are performed by utilizing the signed-digit representation. The divider is implemented with a regularly aligned pipeline structure called a systolic array. The processing element of the systolic array is designed using several logic gates unique to the SFQ circuits, to reduce the number of pipeline stages. As a result, high throughput and low latency is achieved with a small circuit size. The throughput approaches the maximum throughput of serial processing. A 4-bit divider was fabricated using the 2.5-kA/cm2niobium process technology, and successful operation up to 19 GHz was demonstrated.
We investigate a Goldschmidt's single flux quantum (SFQ) floating-point divider that is suitable for the implementation using the bit-serial pipelined SFQ circuit. We designed the bit-serial SFQ divider that outputs the 11-bit quotient. The simulation results show correct operation at the frequency of 50-GHz and bias margin of 80%–125%. We also estimated dependence of latency and the number of Josephson junctions on accuracy of outputs. According to the estimation, double-precision SFQ divider can be designed using 27 000 Josephson junctions, which can be implemented on one chip using the current SFQ circuit fabrication technology. Because of the small circuit area and multiplier-based hardware architecture, the investigated divider can be applied to build an SFQ graphical processing unit.
We have been developing the floating-point unit (FPU) based on single-flux-quantum (SFQ) logic toward a highspeed and low-power superconducting graphical processing unit. The floating-point divider is the most complicated circuit element of the SFQ FPU. We designed the SFQ floating-point divider on the basis of Goldschmidt's algorithm, which is one of multiplicative hardware algorithms for division. Because the multiplies in the divider can be used for multiplication in the FPU by employing the multiplicative division algorithm, the FPU can be efficiently designed by using the designed floating-point divider. We show the circuit scale estimation of the FPU that uses the designed divider as a function on floating-point precision. We measured the 4-bit and 11-bit SFQ floating-point dividers implemented by the AIST 10 kA/cm2Nb advanced process. The 11-bit SFQ floating- point divider is composed of 8091 Josephson junctions and can be applied to half-precision FPU. We confirmed correct operation of the 4-bit SFQ divider by low-frequency function test.
Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.
We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.
We are developing a large-scale reconfigurable data path (LSRDP) using single-flux-quantum (SFQ) circuits as a fundamental technology that can overcome the power-consumption and memory-wall problems in CMOS microprocessors in future high-end computing systems. An SFQ LSRDP is composed of several thousands of SFQ floating-point units connected by reconfigurable SFQ network switches to achieve high performance with low power consumption. In this study, we designed and implemented an SFQ floating-point multiplier (FPM), which is one of the key components of the SFQ LSRDP. We designed a systolic-array bit-serial half-precision FPM using the 2.5 kA/cm2Nb process. The resultant circuit area and number of Josephson junctions are 6.22 mm times 3.78 mm and 11044, respectively. The designed clock frequency is 25 GHz. We tested the circuit and confirmed the correct operation of the FPM by on-chip high-speed tests.
We propose a new design approach for high- throughput arithmetic circuits based on state transitions using single-flux-quantum (SFQ) logic circuits. Microprocessors have several complex interconnects in datapath including loops of data, to which only one SFQ pulse is allowed to be confined, and the loops can spoil the high-throughput nature of SFQ circuits. In our new approach, we regard an arithmetic circuit with loops as a sequential logic circuit, and we use nondestructive readout gates (NDROs) as storage elements of the internal state. We can eliminate the loops and achieve high throughput by translating calculations into transitions of the state stored in the NDROs. We have implemented a bit-serial adder with the proposed approach, and demonstrated 36-GHz operations using the niobium 2.5-kA/cm2standard process technology.