Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

Study on Single Flux Quantum Floating-Point Divider Based on Goldschmidt's Algorithm

Akiyoshi Sanada, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Mar 18, 2019• 9 citations
Publisher

Abstract

We investigate a Goldschmidt's single flux quantum (SFQ) floating-point divider that is suitable for the implementation using the bit-serial pipelined SFQ circuit. We designed the bit-serial SFQ divider that outputs the 11-bit quotient. The simulation results show correct operation at the frequency of 50-GHz and bias margin of 80%–125%. We also estimated dependence of latency and the number of Josephson junctions on accuracy of outputs. According to the estimation, double-precision SFQ divider can be designed using 27 000 Josephson junctions, which can be implemented on one chip using the current SFQ circuit fabrication technology. Because of the small circuit area and multiplier-based hardware architecture, the investigated divider can be applied to build an SFQ graphical processing unit.

DOI
10.1109/tasc.2019.2902800

Related papers

Measurement of Single-Flux-Quantum Floating-Point Divider Based on Goldschmidt's Algorithm

Yuki Yamanashi, Akiyoshi Sanada, Nobuyuki Yoshikawa

We have been developing the floating-point unit (FPU) based on single-flux-quantum (SFQ) logic toward a highspeed and low-power superconducting graphical processing unit. The floating-point divider is the most complicated circuit element of the SFQ FPU. We designed the SFQ floating-point divider on the basis of Goldschmidt's algorithm, which is one of multiplicative hardware algorithms for division. Because the multiplies in the divider can be used for multiplication in the FPU by employing the multiplicative division algorithm, the FPU can be efficiently designed by using the designed floating-point divider. We show the circuit scale estimation of the FPU that uses the designed divider as a function on floating-point precision. We measured the 4-bit and 11-bit SFQ floating-point dividers implemented by the AIST 10 kA/cm2Nb advanced process. The 11-bit SFQ floating- point divider is composed of 8091 Josephson junctions and can be applied to half-precision FPU. We confirmed correct operation of the 4-bit SFQ divider by low-frequency function test.

IEEE International Superconductive Electronics Conference (ISEC)•Jul 1, 2019•0 citations

A High-Throughput Single-Flux Quantum Floating-Point Serial Divider Using the Signed-Digit Representation

Masamitsu Tanaka, Koji Obata, Kazumasa Takagi +3 more

We propose a floating-point serial divider for a single-flux quantum (SFQ) logic implementation based on a hardware algorithm of division using subtract and shift operations. Fast serial calculations are performed by utilizing the signed-digit representation. The divider is implemented with a regularly aligned pipeline structure called a systolic array. The processing element of the systolic array is designed using several logic gates unique to the SFQ circuits, to reduce the number of pipeline stages. As a result, high throughput and low latency is achieved with a small circuit size. The throughput approaches the maximum throughput of serial processing. A 4-bit divider was fabricated using the 2.5-kA/cm2niobium process technology, and successful operation up to 19 GHz was demonstrated.

IEEE Transactions on Applied Superconductivity•May 27, 2009•6 citations

Design, Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Multiplier

Hideo Hara, Koji Obata, Park Heejoung +8 more

We are developing a large-scale reconfigurable data path (LSRDP) using single-flux-quantum (SFQ) circuits as a fundamental technology that can overcome the power-consumption and memory-wall problems in CMOS microprocessors in future high-end computing systems. An SFQ LSRDP is composed of several thousands of SFQ floating-point units connected by reconfigurable SFQ network switches to achieve high performance with low power consumption. In this study, we designed and implemented an SFQ floating-point multiplier (FPM), which is one of the key components of the SFQ LSRDP. We designed a systolic-array bit-serial half-precision FPM using the 2.5 kA/cm2Nb process. The resultant circuit area and number of Josephson junctions are 6.22 mm times 3.78 mm and 11044, respectively. The designed clock frequency is 25 GHz. We tested the circuit and confirmed the correct operation of the FPM by on-chip high-speed tests.

IEEE Transactions on Applied Superconductivity•Jun 1, 2009•29 citations

Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process

Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa +4 more

Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.

IEICE Transactions on Electronics•Jan 1, 2014•13 citations

60-GHz demonstration of an SFQ half-precision bit-serial floating-point adder using 10 kA/cm2 Nb process

T. Kato, Yuki Yamanashi, Nobuyuki Yoshikawa +4 more

We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. In the LSRDP, an SFQ floating-point adder (FPA) is one of the main and most complicated circuit blocks. In our previous study, we implemented an SFQ half-precision (16-bit) bit-serial FPA using the ISTEC 2.5 kA/cm2standard process, and demonstrated the correct operations at 24 GHz by on-chip high-speed tests. In this study, we designed and implemented an SFQ half-precision bit-serial FPA using a cell library for the AIST 10 kA/cm2Nb nine-metal-layer process (ADP2), and carried out on-chip high speed tests. The designed FPA contains 9661 Josephson junctions and occupies a circuit area of 12.95 mm2. Its target operation frequency is 50 GHz. We have demonstrated the correct operation of the FPA at the maximum frequency of 62 GHz although there is a functional error in the design. The measured DC bias margin ranges from 102% to 108% at 50 GHz operation. The total power consumption is measured to be 2.9 mW.

IEEE International Superconductive Electronics Conference (ISEC)•Jul 1, 2013•18 citations

Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm$^{2}$ Nb Process

Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka +6 more

We have been developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. The SFQ floating-point adder (FPA) is one of the principal and most complicated circuit blocks in an LSRDP. In this study, we designed and implemented component circuits of an SFQ bit-serial half-precision FPA using the cell library for a 10-kA/cm2Nb process and performed on-chip high-speed tests. We demonstrated correct operation of the four-bit shifter for the significand at the clock frequencies of up to 76 GHz. The dependence of the measured DC bias margin on the operating frequency agrees reasonably well with the margin calculated using a digital simulation. The operation of the normalizer for the significand has been also confirmed at low speeds.

IEEE Transactions on Applied Superconductivity•Jan 7, 2011•13 citations
We investigate a Goldschmidt's single flux quantum (SFQ) floating-point divider that is suitable for the implementation using the bit-serial pipelined SFQ circuit. We designed the bit-serial SFQ divider that outputs the 11-bit quotient. The simulation results show correct operation at the frequency of 50-GHz and bias margin of 80%–125%. We also estimated dependence of latency and the number of Josephson junctions on accuracy of outputs. According to the estimation, double-precision SFQ divider can be designed using 27 000 Josephson junctions, which can be implemented on one chip using the current SFQ circuit fabrication technology. Because of the small circuit area and multiplier-based hardware architecture, the investigated divider can be applied to build an SFQ graphical processing unit.
We have been developing the floating-point unit (FPU) based on single-flux-quantum (SFQ) logic toward a highspeed and low-power superconducting graphical processing unit. The floating-point divider is the most complicated circuit element of the SFQ FPU. We designed the SFQ floating-point divider on the basis of Goldschmidt's algorithm, which is one of multiplicative hardware algorithms for division. Because the multiplies in the divider can be used for multiplication in the FPU by employing the multiplicative division algorithm, the FPU can be efficiently designed by using the designed floating-point divider. We show the circuit scale estimation of the FPU that uses the designed divider as a function on floating-point precision. We measured the 4-bit and 11-bit SFQ floating-point dividers implemented by the AIST 10 kA/cm2Nb advanced process. The 11-bit SFQ floating- point divider is composed of 8091 Josephson junctions and can be applied to half-precision FPU. We confirmed correct operation of the 4-bit SFQ divider by low-frequency function test.
We propose a floating-point serial divider for a single-flux quantum (SFQ) logic implementation based on a hardware algorithm of division using subtract and shift operations. Fast serial calculations are performed by utilizing the signed-digit representation. The divider is implemented with a regularly aligned pipeline structure called a systolic array. The processing element of the systolic array is designed using several logic gates unique to the SFQ circuits, to reduce the number of pipeline stages. As a result, high throughput and low latency is achieved with a small circuit size. The throughput approaches the maximum throughput of serial processing. A 4-bit divider was fabricated using the 2.5-kA/cm2niobium process technology, and successful operation up to 19 GHz was demonstrated.
We are developing a large-scale reconfigurable data path (LSRDP) using single-flux-quantum (SFQ) circuits as a fundamental technology that can overcome the power-consumption and memory-wall problems in CMOS microprocessors in future high-end computing systems. An SFQ LSRDP is composed of several thousands of SFQ floating-point units connected by reconfigurable SFQ network switches to achieve high performance with low power consumption. In this study, we designed and implemented an SFQ floating-point multiplier (FPM), which is one of the key components of the SFQ LSRDP. We designed a systolic-array bit-serial half-precision FPM using the 2.5 kA/cm2Nb process. The resultant circuit area and number of Josephson junctions are 6.22 mm times 3.78 mm and 11044, respectively. The designed clock frequency is 25 GHz. We tested the circuit and confirmed the correct operation of the FPM by on-chip high-speed tests.
Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.
We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. In the LSRDP, an SFQ floating-point adder (FPA) is one of the main and most complicated circuit blocks. In our previous study, we implemented an SFQ half-precision (16-bit) bit-serial FPA using the ISTEC 2.5 kA/cm2standard process, and demonstrated the correct operations at 24 GHz by on-chip high-speed tests. In this study, we designed and implemented an SFQ half-precision bit-serial FPA using a cell library for the AIST 10 kA/cm2Nb nine-metal-layer process (ADP2), and carried out on-chip high speed tests. The designed FPA contains 9661 Josephson junctions and occupies a circuit area of 12.95 mm2. Its target operation frequency is 50 GHz. We have demonstrated the correct operation of the FPA at the maximum frequency of 62 GHz although there is a functional error in the design. The measured DC bias margin ranges from 102% to 108% at 50 GHz operation. The total power consumption is measured to be 2.9 mW.
Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm2^{2}2 Nb Process
We have been developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. The SFQ floating-point adder (FPA) is one of the principal and most complicated circuit blocks in an LSRDP. In this study, we designed and implemented component circuits of an SFQ bit-serial half-precision FPA using the cell library for a 10-kA/cm2Nb process and performed on-chip high-speed tests. We demonstrated correct operation of the four-bit shifter for the significand at the clock frequencies of up to 76 GHz. The dependence of the measured DC bias margin on the operating frequency agrees reasonably well with the margin calculated using a digital simulation. The operation of the normalizer for the significand has been also confirmed at low speeds.