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IEEE Transactions on Applied Superconductivity

Impedance Matching of Microstrip Inductors in Digital Superconductive Electronics

Thomas Ortlepp, Friedrich Uhlmann

Published Jun 1, 2009• 12 citations
Publisher

Abstract

State-of-the-art RSFQ circuits consist of Josephson junctions, inductances and bias current sources, where the inductances are practically used as functional elements. Even more, their value defines the functionality and therefore the conventional design process requires strict conditions for the wiring between Josephson junctions. The present design and optimization process does not take into account their parasitic capacitances to ground. This becomes an important issue for ultra fast applications above 100 GHz, but also for circuits dedicated to control quantum electronics. We report on a theoretical and experimental investigation of the influence of ground capacitances. The impedance matching between the connecting microstrip lines and the Josephson junction is a key issue for the correct operation of these circuits. We performed circuit simulations and collected experimental data of correct and incorrect operating circuits to derive design criteria. The critical reflection coefficient is found to be 0.35 and the particular design must use a smaller value for transfer and a larger value for storage of SFQ pulses, respectively.

DOI
10.1109/tasc.2009.2019284

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State-of-the-art RSFQ circuits consist of Josephson junctions, inductances and bias current sources, where the inductances are practically used as functional elements. Even more, their value defines the functionality and therefore the conventional design process requires strict conditions for the wiring between Josephson junctions. The present design and optimization process does not take into account their parasitic capacitances to ground. This becomes an important issue for ultra fast applications above 100 GHz, but also for circuits dedicated to control quantum electronics. We report on a theoretical and experimental investigation of the influence of ground capacitances. The impedance matching between the connecting microstrip lines and the Josephson junction is a key issue for the correct operation of these circuits. We performed circuit simulations and collected experimental data of correct and incorrect operating circuits to derive design criteria. The critical reflection coefficient is found to be 0.35 and the particular design must use a smaller value for transfer and a larger value for storage of SFQ pulses, respectively.
The Rapid Single Flux Quantum (RSFQ) technique is regarded as one of the most promising electronics due to its extremely high operating speed and low power consumption. Middle-scale RSFQ applications operating at multigigahertz frequency have recently been reported on. At such high operating frequencies, the on-chip interconnects start to play a limiting role for the performance of the densely packaged digital circuits. Our previous studies have theoretically investigated the parasitic coupling effects between superconductive microstrip transmission lines and conclusions have been drawn about the critical coupling levels of several typical microstrip geometries. Here, basic RSFQ structures are investigated experimentally, which contain a Josephson transmission line stage with large inductance and can either trap or pass SFQ pulses. These structures are incorporated in critical microstrip layouts, thus being subjected to parasitic coupling. The bias levels are monitored at which the structures start to pass the SFQ pulses with and without coupling influences. Thus, the conclusions of our previous theoretical investigations are verified experimentally.
The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of ±29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm2technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.
Bias lines routed over a ground plane naturally form microstrip lines associated with the presence of a capacitance. This can lead to unwanted resonances when coupled to Josephson junctions. This article presents an electrical model of a shunted Josephson junction with its bias lines and pads, fabricated with the 1 kA/cm2rapid single flux quantum niobium process of the FLUXONICS foundry (J. Kunert, 2013), (J. Kunert, 2017). A T-model is used to simulate the microwave behavior of the bias line, predict resonances and design resonance-free superconducting circuits. The I-V characteristics of three shunted Josephson junctions have been obtained from time-domain simulations done with Josephson SIMulator (JSIM) (E. S. Fang and T. Van Duzer, 1989) and show a good match with the experimentally observed resonance at 230 GHz up to the normal resistance branch, measured at 4.2 K. The influence of the position and value of a series resistor placed on bias lines is studied to damp unwanted resonances at the junction.
Along with the improvement of integration and the requirement of high-speed operation, the passive transmission line (PTL) plays a significant role in superconducting integrated circuits due to its intrinsic advantage of extremely low propagation delay and low signal loss in long-distance transmission. Good impedance matching is critical to reduce the signal reflection in the transmission line and maximize the power transferred. Based on the PTL wiring layer selection under SIMIT-Nb03 process, we studied the equivalent input/output impedance for Josephson junction (JJ) at the IO port and explored a method of impedance matching in rapid-single-flux-quantum circuits by adjusting the Stewart McCumber parameterβC{\beta }_{\bm{C}}βC​of the JJ in the design of the PTL's driver and receiver. Furthermore, the accompanying influence from JJ's modifiedβC{\beta }_{\bm{C}}βC​on the performance of the driver and receiver is evaluated to maximize the profit of the functional circuits. The common-used serial resistor is removed to obtain a balanced bias margin for the PTL circuits. The proposed PTL has been designed and tested based on SIMIT-Nb03 fabrication process. In total,$ \pm $30% bias margin for the PTL is achieved at low frequency and high frequency (40 GHz) contrast tests, including operation speed and transmission length as test vector. Additionally, a frequency sweep for 1 mm PTL is performed by the designed ring oscillator on the chip. The maximum working frequency is up to 129 GHz, with a margin duration of 8%.
Single-flux-quantum (SFQ) digital circuits are mostly based on cells that rely on reliable foundry processes that make use of a superconducting ground plane as a reference for the active elements and the microstrip line interconnects. The quantum of magnetic flux h/2e, associated with the binary information, corresponds to a magnetic field energy density that needs to be localized in space to limit interactions between adjacent cells. In other words, mutual inductances can harm the proper behaviour of circuits unless they are taken carefully into account during the design phase. We studied extensively the Josephson transmission line cell with different geometrical configurations of the ground plane and bias pads. We found with the use of InductEx that the return current sometimes follows paths that are far from what intuition tells, which can lead to nonoptimized designs. In this paper, we emphasize the limitations due to the presence of external or internal magnetic fields. Then, we compare obtained performances with the ones with optimized geometries for which the presence of the magnetic field is taken into account from the design phase.
The increasing complexity of modern superconductive circuits, and single flux quantum (SFQ) circuits in particular, has made the issue of coupling noise of growing importance. Limited metal resources within superconductive circuits have exacerbated this issue. In this article, the different sources of coupling noise within SFQ circuits are described. Coupling noise among inductors, routing striplines, and bias microstriplines within SFQ circuits degrade performance while decreasing margins. In this article, inductive and capacitive coupling between the different layers are characterized. Inductive coupling models between different layers in the MIT LL SFQ5ee process match experimental data within 3%. The dependence of inductive coupling on the thickness of the oxide and metal layer is also discussed. An understanding of inductive and capacitive coupling can determine the minimum physical distance between lines. In addition, tradeoffs exist among inductive coupling, capacitive coupling, layout complexity, and the vias between ground layers. The different coupling sources are characterized, and guidelines are provided to enhance the automated routing process.