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IEEE Transactions on Applied Superconductivity

Investigation of the Parasitic Coupling Effects in Densely Packaged RSFQ Digital Circuits

Boyko Dimov, M. Khabipov, D Balashov, C.M. Brandt, F.-I. Buchholz, J. Niemeyer, Thomas Ortlepp, Friedrich Uhlmann

Published Jun 1, 2005• 2 citations
Publisher

Abstract

The Rapid Single Flux Quantum (RSFQ) technique is regarded as one of the most promising electronics due to its extremely high operating speed and low power consumption. Middle-scale RSFQ applications operating at multigigahertz frequency have recently been reported on. At such high operating frequencies, the on-chip interconnects start to play a limiting role for the performance of the densely packaged digital circuits. Our previous studies have theoretically investigated the parasitic coupling effects between superconductive microstrip transmission lines and conclusions have been drawn about the critical coupling levels of several typical microstrip geometries. Here, basic RSFQ structures are investigated experimentally, which contain a Josephson transmission line stage with large inductance and can either trap or pass SFQ pulses. These structures are incorporated in critical microstrip layouts, thus being subjected to parasitic coupling. The bias levels are monitored at which the structures start to pass the SFQ pulses with and without coupling influences. Thus, the conclusions of our previous theoretical investigations are verified experimentally.

DOI
10.1109/tasc.2005.849859

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The Rapid Single Flux Quantum (RSFQ) technique is regarded as one of the most promising electronics due to its extremely high operating speed and low power consumption. Middle-scale RSFQ applications operating at multigigahertz frequency have recently been reported on. At such high operating frequencies, the on-chip interconnects start to play a limiting role for the performance of the densely packaged digital circuits. Our previous studies have theoretically investigated the parasitic coupling effects between superconductive microstrip transmission lines and conclusions have been drawn about the critical coupling levels of several typical microstrip geometries. Here, basic RSFQ structures are investigated experimentally, which contain a Josephson transmission line stage with large inductance and can either trap or pass SFQ pulses. These structures are incorporated in critical microstrip layouts, thus being subjected to parasitic coupling. The bias levels are monitored at which the structures start to pass the SFQ pulses with and without coupling influences. Thus, the conclusions of our previous theoretical investigations are verified experimentally.
The reduction of the critical current density in rapid single-flux quantum (RSFQ) circuits enables new application fields, like quantum computing and photonic detector readout. The low current density fabrication process creates new design challenges, such as lower stability against thermal fluctuations, violation of the lumped elements condition for microstrip inductances and increased sensitivity to the technological spread. To overcome these issues, we suggest a passive phase shifter as a promising alternative technique for superconductive phase dropping in the RSFQ electronics. Here, we study experimentally their applicability in high-speed RSFQ digital circuits. Conclusions are drawn about the impact of the passive phase shifters on the complexity, the speed and the bit error rate of the investigated RSFQ circuits. We demonstrate the successful operation of different circuits with implemented passive phase shifters at low and high speeds.
Within the classical Rapid Single-Flux Quantum (RSFQ) digital designs, the superconductive phase dropping necessary for the optimal SFQ data processing is realized with short sections of transmission lines serving as lumped inductances. This approach meets several hard restrictions about some promising future RSFQ applications requiring a drastic reduction of the junctions' critical currents. In this paper, we analyse these restrictions, and present an alternative and experimentally verified technique for superconductive phase dropping, which is compatible with any RSFQ fabrication technology. This technique provides compact and robust RSFQ digital circuits with highly improved fabrication yield.
AbstractSuperconducting digital technology based on Rapid Single Flux Quantum (RSFQ) logic offers a 50 times faster clock rate and 100 times less on chip power consumption than today's mainstream semiconductor electronics. This technology is attractive for many applications and in particular for Digital Signal Processing (DSP). The applications of the RSFQ DSPs are numerous and include multi-user detection in spread spectrum system, channel equalization for Multi-in, Multi-out (MIMO) systems, and blind detection and signal tracking for signal intelligence.At Chalmers we are developing a hybrid DSP with target performance of 30 giga operations per second. It consists of an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory, and an external semiconductor memory. The development of the complex high speed cryogenic digital system requires interface, packaging and testing solutions. The main difficulties are due to the 4 K operational temperature, the high magnetic field sensitivity of the RSFQ circuits, the multi-channel high bandwidth interface required in the hybrid architecture, and the high speed RSFQ digital core. The key steps towards addressing each of these problems are the subject of this thesis. The main emphasis is put on the experimental testing and interfacing of superconductor electronics. A large part of the work is connected to the experimental verification of DSP components and their incremental improvement towards functionality. The RSFQ circuits tested were fabricated using the four-metal layer VLSI processes available from NGST(8 kA/cm^2 Josephson junction critical current) and HYPRES (both 1 kA/cm^2 and HYPRES 4.5 kA/cm^2. The main results of the work are demonstrations of the RSFQ cache memory with more than 2,000 Josephson junctions, 33.5 GHz operation of the digital clock controller, and 20.48 GHz operation of the autocorrelator. In addition, various experiments have been done for investigation of parasitic effects in RSFQ circuits such as flux trapping and influence of the high current bias lines.At the final stage of the work, a unique high bandwidth 4 K cryocooler based experimental setup has been developed. The system, developed in close cooperation with Hypres Inc. USA, has 40 high speed I/Os with bandwidth of 2 Gbps, 64 DC bias channels, 4 high frequency clock lines, and 4 auxiliary control lines. It supports exchangeable test units for 10 mm x 10 mm and 20 mm x 20 mm Multi Chip Module (MCM) carriers. The availability of such a system is critical to demonstration of the hybrid DSP prototype and future commercialization.
The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of ±29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm2technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.
State-of-the-art RSFQ circuits consist of Josephson junctions, inductances and bias current sources, where the inductances are practically used as functional elements. Even more, their value defines the functionality and therefore the conventional design process requires strict conditions for the wiring between Josephson junctions. The present design and optimization process does not take into account their parasitic capacitances to ground. This becomes an important issue for ultra fast applications above 100 GHz, but also for circuits dedicated to control quantum electronics. We report on a theoretical and experimental investigation of the influence of ground capacitances. The impedance matching between the connecting microstrip lines and the Josephson junction is a key issue for the correct operation of these circuits. We performed circuit simulations and collected experimental data of correct and incorrect operating circuits to derive design criteria. The critical reflection coefficient is found to be 0.35 and the particular design must use a smaller value for transfer and a larger value for storage of SFQ pulses, respectively.
Rapid single flux quantum (RSFQ) electronics is based on the Josephson junction as an active switching element. In standard RSFQ circuits its switching energy is much lower than the static power consumption caused by the resistive current distribution network. Due to this thermal heating of the chip, the maximum number of junctions on a single chip is limited to about 1 million. The frequency-dependent contribution to power dissipation from junction switchings is only about 2 percent of the static one. This fact limits the direct construction of VLSI systems for high-performance computing as well as small-scale circuit applications in the vicinity of ultra-sensitive detectors or even quantum circuits. We present an assessment of different approaches for reducing the static power consumption by investigating the potential of inductive bias distribution networks as well as reduced critical currents. We analyse the operation stability of simple digital circuits with 5 times smaller critical currents at 4.2 K. The combination of the reduced critical currents and inductive biasing can provide digital superconductive circuits with significantly reduced static power consumption.