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Superconductor Science and Technology

Implementation of superconductive passive phase shifters in high-speed integrated RSFQ digital circuits

Boyko Dimov, D Balashov, M. Khabipov, Thomas Ortlepp, F-Im Buchholz, Alexander B Zorin, J. Niemeyer, Friedrich Uhlmann

Published Feb 25, 2008• 10 citations
Publisher

Abstract

The reduction of the critical current density in rapid single-flux quantum (RSFQ) circuits enables new application fields, like quantum computing and photonic detector readout. The low current density fabrication process creates new design challenges, such as lower stability against thermal fluctuations, violation of the lumped elements condition for microstrip inductances and increased sensitivity to the technological spread. To overcome these issues, we suggest a passive phase shifter as a promising alternative technique for superconductive phase dropping in the RSFQ electronics. Here, we study experimentally their applicability in high-speed RSFQ digital circuits. Conclusions are drawn about the impact of the passive phase shifters on the complexity, the speed and the bit error rate of the investigated RSFQ circuits. We demonstrate the successful operation of different circuits with implemented passive phase shifters at low and high speeds.

DOI
10.1088/0953-2048/21/4/045007

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The reduction of the critical current density in rapid single-flux quantum (RSFQ) circuits enables new application fields, like quantum computing and photonic detector readout. The low current density fabrication process creates new design challenges, such as lower stability against thermal fluctuations, violation of the lumped elements condition for microstrip inductances and increased sensitivity to the technological spread. To overcome these issues, we suggest a passive phase shifter as a promising alternative technique for superconductive phase dropping in the RSFQ electronics. Here, we study experimentally their applicability in high-speed RSFQ digital circuits. Conclusions are drawn about the impact of the passive phase shifters on the complexity, the speed and the bit error rate of the investigated RSFQ circuits. We demonstrate the successful operation of different circuits with implemented passive phase shifters at low and high speeds.
A vital precondition for the realization of rapid single-flux quantum (RSFQ) digital circuits with reduced critical currents of the Josephson junctions is the implementation of an efficient technique for superconductive phase dropping. In this paper, we present a novel phase shifting element consisting of a miniature superconductive ring located over a ground plane hole. Contrary to the solutions reported up to now, this topology can be simply integrated within complex digital RSFQ circuits realized with conventional fabrication technology.
Within the classical Rapid Single-Flux Quantum (RSFQ) digital designs, the superconductive phase dropping necessary for the optimal SFQ data processing is realized with short sections of transmission lines serving as lumped inductances. This approach meets several hard restrictions about some promising future RSFQ applications requiring a drastic reduction of the junctions' critical currents. In this paper, we analyse these restrictions, and present an alternative and experimentally verified technique for superconductive phase dropping, which is compatible with any RSFQ fabrication technology. This technique provides compact and robust RSFQ digital circuits with highly improved fabrication yield.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>
We have found that the size of some rapid single-flux quantum (RSFQ) logic cells based on conventional 0-type Josephson junctions can be significantly reduced by using a π-type junction as a phase shifter in passive (nonswitching) mode. In comparison with the recently suggested active (switching) π-junctions mode, the passive mode offers much greater operation margins for their critical current Icπ. This gives π-junctions a chance to be implemented in RSFQ designs in the near future. As an example, we have simulated the operation of a toggle flip flop with zero-geometrical inductance of the fluxon storage loop. Simulations show that the parametric inductance of the π-junction and its normal resistance Rn form a low-pass filter, which sets the low limit for π-junctions IcπRn product, but offers a wide range of variations of the other parameters. The possible reduction of RSFQ cell size by using π-junctions opens the way to scale superconducting logic circuits down to the submicron dimensions.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.