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IEEE Transactions on Applied Superconductivity

Demonstration of RSFQ digitizer on a multichip module

Joonhee Kang, Deepnarayan Gupta, Steven B. Kaplan

Published Sep 1, 2002• 2 citations
Publisher

Abstract

A 1-b slice of a rapid single-flux quantum (RSFQ) digitizer with interchip communications on a multichip module (MCM) has been successfully designed, fabricated using 3-/spl mu/m Nb technology, and tested. We placed a flash comparator followed by an enable switch and an MCM transmitter circuit on one side of the chip, and an MCM receiver circuit followed by a memory buffer on the other side. The 5 /spl times/ 5 mm chip was flip-chip mounted on a 10 /spl times/ 10 mm carrier chip by a solder bump technique. During circuit operation, the comparator output signal and the clock signal left the chip, moved to the carrier chip, and returned back to the chip into the memory buffer. We operated the circuit with a beat frequency technique where the data input frequency was slightly off from the clock frequency by the beat frequency of 10 kHz. The circuit operated correctly up to 10 GHz. The critical circuit operation margin was observed to be the bias current to the SQUID in the MCM receiver circuit and was about /spl plusmn/6% at 10 GHz.

DOI
10.1109/tasc.2002.801818

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IEEE Transactions on Applied Superconductivity•Mar 1, 2001•7 citations
A 1-b slice of a rapid single-flux quantum (RSFQ) digitizer with interchip communications on a multichip module (MCM) has been successfully designed, fabricated using 3-/spl mu/m Nb technology, and tested. We placed a flash comparator followed by an enable switch and an MCM transmitter circuit on one side of the chip, and an MCM receiver circuit followed by a memory buffer on the other side. The 5 /spl times/ 5 mm chip was flip-chip mounted on a 10 /spl times/ 10 mm carrier chip by a solder bump technique. During circuit operation, the comparator output signal and the clock signal left the chip, moved to the carrier chip, and returned back to the chip into the memory buffer. We operated the circuit with a beat frequency technique where the data input frequency was slightly off from the clock frequency by the beat frequency of 10 kHz. The circuit operated correctly up to 10 GHz. The critical circuit operation margin was observed to be the bias current to the SQUID in the MCM receiver circuit and was about /spl plusmn/6% at 10 GHz.
Chip-to-chip propagation of a single flux quantum (SFQ) pulse has been demonstrated using an active multichip module (MCM) technique in which active transmitters and receivers are integrated on an MCM substrate as well as on a chip. A chip-to-chip SFQ transfer circuit has been designed and implemented by a standard Nb-trilayer process and solder-bumped flip-chip technology. The correct operation of the circuit has been confirmed by low-frequency testing. Experimental margins for the global factor for bias currents have been as large as /spl plusmn/33%.
We have developed an interchip data transmission scheme through passive transmission lines on a multi-chip-module (MCM) carrier and 100-/spl mu/m solder bump bonds. In rapid single flux quantum (RSFQ) logic, digital data are in the form of single flux quantum (SFQ) pulses. A reliable scheme for transmission of SFQ pulses through non-superconducting solder bumps between chips through a passive MCM substrate is yet to be established. Therefore, we have devised a scheme that converts SFQ pulses into toggles in a voltage waveform for interchip transmission. Data in the form of SFQ pulses are reconstructed from this voltage waveform using a sensitive quantizing pulse receiver. Our objective is to eliminate the need for amplification of the transmitted signal. This is achieved by increasing the receiver sensitivity. However, a sensitive receiver, a dc SQUID, may produce more than one SFQ pulse for each rising/falling edge of the voltage waveform. A simple circuit, pulse resurrection logic (PRL), is employed to discard any extra SFQ pulses. Together with the sensitive quantizer, the PRL circuit makes our scheme error tolerant. We have demonstrated the receiver operation using 3-/spl mu/m Nb RSFQ circuits at frequencies up to 20 GHz.
We report experimental results on chip-to-chip transfer of single-flux-quantum (SFQ) pulses using an active multichip module (MCM). Josephson transmitters and receivers are integrated on both a chip and an MCM substrate. An MCM consisting of a 4.8-mm chip and an 8.2-mm MCM substrate was fabricated using a 1.6-kA/cm/sup 2/ Nb-trilayer process and a solder-bumped flip-chip bonding technology. The correct operation of the circuit was confirmed by low-speed testing. Bit-error rate (BER) of the circuit was measured down to 10/sup -5/, and extrapolation of the error-function fits suggested a very small BER, lower than 10/sup -200/, at the optimum bias point. Experimental margins on the bias voltage were as large as /spl plusmn/34%.
A new generation of the Josephson digital circuits-rapid single flux quantum (RSFQ) devices-based on overdamped externally shunted high quality Nb-AlO x -Nb tunnel junctions have been designed, fabricated and experimentally investigated. All-refractory material 11-layer 5 mu m integrated technology has been successfully employed for the preparation of the RSFQ microcircuits. The T flip-flop has been demonstrated to operate properly up to clock frequencies of 100 GHz at 25% margins. The proper operation of the buffer stage for a one-directional SFQ pulse transmission at clock frequencies up to 125 GHz has been achieved. The possibilities to convert the information from the usual DC form to SFQ and vice versa have been demonstrated. An output signal in an SFQ/DC converter as high as 220 mu V has been measured. A new counter type A/D converter which includes a comparator and reversible binary counter with DC outputs has been fabricated and tested. The proposed ADC seems to be very promising for high-accuracy measurement of medium-bandwidth signals. The possibilities of creating a number of SFQ devices with outstanding parameters are discussed.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>
The paper presents the determination of the high-frequency performance of Rapid Single Flux Quantum (RSFQ) circuits fabricated in superconductor-insulator-normal metal-insulator-superconductor (SINIS) technology. Circuits of different designs have been realized and were experimentally investigated, including specially designed T flip-flop (TFF) structures and circuits consisting of a switch terminated in Josephson transmission lines. For TFF circuits, the operational functionality was investigated in the frequency range from dc up to nearly 200 GHz. Two frequency domains were found. In the first domain, ranging up to frequencies of 80 GHz (f/sub C//spl cong/Y/sub C///spl Phi//sub 0/), correct digital operation of the device was ascertained. Beyond this range a second domain was found, ranging to nearly 200 GHz, for which quasi-analog frequency dividing is assumed. The bias current margins are /spl plusmn/30% at 40 GHz and /spl plusmn/15% between 130 GHz and 200 GHz. For circuits consisting of a switch, the operational functionality was proved in the frequency range from dc up to 50 GHz, with bias current margins of more than /spl plusmn/20%. The critical current density of the circuits is j/sub C//spl cong/750 A/cm/sup 2/. The smallest junction area is about A=12 /spl mu/m/sup 2/, and the characteristic voltage is V/sub C/=170 /spl mu/V.