Cryogenic Phase Locking Loop System for Flux-Flow Oscillator

Andrey V. Khudchenko, V. P. Koshelets, Pavel N. Dmitriev, An. B. Ermakov, O. M. Pylypenko, Pavel A. Yagoubov

Published Apr 1, 2008• 3 citations

Abstract

Recently a cryogenic phase detector (CPD) based on a superconductor-insulator-superconductor junction has been proposed and preliminary tested. The CPD is initially intended for phase locking of a Flux-Flow Oscillator (FFO) in a Superconducting Integrated Receiver (SIR). A model to describe coupling between the CPD and the FFO has been developed and experimentally verified. We present a design of the Cryogenic Phase Locking Loop (CPLL) system implemented for the SIR and discuss the results of the CPLL experimental tests. The effective bandwidth of the CPLL system exceeds 25 MHz at the reference oscillator frequency of 400 MHz. The CPLL bandwidth considerably surpasses that of the room-temperature PLL system, for which it is limited to 12 MHz by inevitable delays in the long cables and semiconductor devices. The novel CPLL system can phase-lock more than 50% of the emitted by FFO power even if the free-running FFO linewidth is about 10 MHz. This fraction of phase-locked power is twice as much as the result of the conventional room-temperature PLL. Such an improvement allows to reduce the FFO phase noise and extend the SIR operation range.

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