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Superconductor Science and Technology

A cryogenic phase locking loop system for a superconducting integrated receiver

Andrey V. Khudchenko, V. P. Koshelets, Pavel N. Dmitriev, An. B. Ermakov, Pavel A. Yagoubov, O. M. Pylypenko

Published Jul 23, 2009• 11 citations
Publisher

Abstract

The authors present a new cryogenic device, an ultrawideband cryogenic phase locking loop system (CPLL). The CPLL was developed for phase locking of a flux-flow oscillator (FFO) in a superconducting integrated receiver (SIR) but can be used for any cryogenic terahertz oscillator. The key element of the CPLL is the cryogenic phase detector (CPD), a recently proposed new superconducting element. The CPD is an innovative implementation of a superconductor– insulator–superconductor tunnel junction. All components of the CPLL reside inside a cryostat at 4.2 K, with the loop length of cables 50 cm and the total loop delay 4.5 ns. So small a delay results in a CPLL synchronization bandwidth as wide as 40 MHz and allows phase locking of more than 60% of the power emitted by the FFO, even for FFO linewidths of about 11 MHz. This percentage of phase locked power is three times that achieved with conventional room temperature PLLs. Such an improvement enables reducing the FFO phase noise and extending the SIR operation range. (Some figures in this article are in colour only in the electronic version)

DOI
10.1088/0953-2048/22/8/085012

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IEEE Transactions on Applied Superconductivity•Jun 1, 2007•49 citations
The authors present a new cryogenic device, an ultrawideband cryogenic phase locking loop system (CPLL). The CPLL was developed for phase locking of a flux-flow oscillator (FFO) in a superconducting integrated receiver (SIR) but can be used for any cryogenic terahertz oscillator. The key element of the CPLL is the cryogenic phase detector (CPD), a recently proposed new superconducting element. The CPD is an innovative implementation of a superconductor– insulator–superconductor tunnel junction. All components of the CPLL reside inside a cryostat at 4.2 K, with the loop length of cables 50 cm and the total loop delay 4.5 ns. So small a delay results in a CPLL synchronization bandwidth as wide as 40 MHz and allows phase locking of more than 60% of the power emitted by the FFO, even for FFO linewidths of about 11 MHz. This percentage of phase locked power is three times that achieved with conventional room temperature PLLs. Such an improvement enables reducing the FFO phase noise and extending the SIR operation range. (Some figures in this article are in colour only in the electronic version)
Recently a cryogenic phase detector (CPD) based on a superconductor-insulator-superconductor junction has been proposed and preliminary tested. The CPD is initially intended for phase locking of a Flux-Flow Oscillator (FFO) in a Superconducting Integrated Receiver (SIR). A model to describe coupling between the CPD and the FFO has been developed and experimentally verified. We present a design of the Cryogenic Phase Locking Loop (CPLL) system implemented for the SIR and discuss the results of the CPLL experimental tests. The effective bandwidth of the CPLL system exceeds 25 MHz at the reference oscillator frequency of 400 MHz. The CPLL bandwidth considerably surpasses that of the room-temperature PLL system, for which it is limited to 12 MHz by inevitable delays in the long cables and semiconductor devices. The novel CPLL system can phase-lock more than 50% of the emitted by FFO power even if the free-running FFO linewidth is about 10 MHz. This fraction of phase-locked power is twice as much as the result of the conventional room-temperature PLL. Such an improvement allows to reduce the FFO phase noise and extend the SIR operation range.
New superconducting element, a cryogenic phase detector (CPD) has been proposed and preliminary tested. The CPD is based on a superconductor-insulator-superconductor junction and initially intended for phase locking of a flux-flow oscillator in a superconducting integrated receiver. First results of the CPD development and study are very encouraging; a sinusoidal response of the CPD has been measured at the variation of the phase shift between input signals. Dependences of the output signal and phase response on the CPD bias voltage have been studied; main parameters of this new device are estimated. Important that the CPD output current well above 10 has been measured at the input signal provided by the harmonic mixer of the integrated receiver and amplified by the existing HEMT-amplifier. Due to the large conversion coefficient this current being supplied to the flux-flow oscillator (FFO) control line is sufficient to directly tune FFO frequency. Obtained data demonstrate that the CPD intrinsically could operate with effective bandwidth more than 100 MHz. Preliminary results of the CPD implementation for the FFO phase locking are presented; possible advantages of such combination are discussed.
A Superconducting Integrated Receiver (SIR) comprises in a single chip a planar antenna combined with a superconductor-insulator-superconductor (SIS) mixer, a superconducting Flux Flow Oscillator (FFO) acting as a Local Oscillator (LO) and a second SIS harmonic mixer (HM) for the FFO phase locking. In this report an overview of the FFO development and optimization is presented. In order to overcome temperature constraints and extend operation frequency of the fully Nb SIR we have developed and studied Nb-AlN-NbN circuits with a gap voltage Vg up to 3.7 mV and extremely low leak currents (Rj/Rn > 30). Continuous tuning of the frequency due to bending and overlapping of the Fiske steps and a possibility to phase lock the Nb-AlN-NbN FFO at any frequency in the range 350-750 GHz has been experimentally demonstrated. After optimization of the FFO design the free-running linewidth between 7 and 1.5 MHz has been measured in the frequency range 350 - 750 GHz, which allows to phase-lock from 50 to 95 % of the emitted FFO power. New designs of the FFO intended for further improvement of its parameters are under development, but even at the present state the Nb-AlN- NbN FFOs are mature enough for practical applications. These achievements enabled development of a 500 - 650 GHz integrated receiver for the Terahertz Limb Sounder (TELIS) project intended for atmosphere study and scheduled to fly on a balloon in 2008.
A new approach to phase-locking of a Flux Flow Oscillator (FFO) (1) in a superconducting integrate d receiver (2, 3) has been proposed and experimentally verified. A ccording to this novel concept, a superconductor-insulator-superconductor (SIS) junction is implemented both for down-conversion of the FFO frequency and for formation of the signal to phase-lock the FFO to the external reference by applying the Harmonic Mixer (HM) output directly to the FFO control line. In ot her words, we introduce a new element of superconductive electronics, which is based on the SIS junction and works as a c ryogenic harmonic phase detector (CHPD). To realize efficient phase-locking of the FFO the HM output signal should be maximized. Value of this signal de pends in a complicated way on the HM bias voltage, frequencies and powers of the local oscillator (LO) and the RF signa ls. We have studied the HM theoretically and calculated 3D dependences of the HM output signal power versus the bias voltage and the LO power. Results of the calculations have been compared with experimental measurements. Good qualitative and quantitative correspondence has been achieved. For demonstration of the FFO phase-locking by the CHPD we have fabricated specially designed samples: all feedback loop elements are integrated on the same chip together w ith the FFO and the CHPD. The FFO frequency should be equal to a harmonic of the LO signal applied to the CHPD. Such a PLL system is expected to be extra wideband due to cons iderable reduction of the loop length. This concept is very promising for building of the multi-pixel SIR array.
In this report an overview of the results on the development of a single-chip superconducting integrated receiver for the Terahertz Limb Sounder (TELIS) balloon project intended to measure a variety of stratosphere trace gases is presented. The Superconducting Integrated Receiver (SIR) comprises in one chip a planar antenna integrated with a superconductor-insulator-superconductor (SIS) mixer, a superconducting Flux Flow Oscillator (FFO) acting as local oscillator (LO) and a second SIS harmonic mixer (HM) for FFO phase locking. As a result of the FFO design optimization a free-running linewidth between 9 and 1.5 MHz has been measured in the frequency range 500-710 GHz resulting in phase-locking of 35 to 95% of the FFO power correspondingly. A new generation of the SIR devices with improved FFO performance and optimized interface between FFO and SIS/HM has been developed and comprehensively tested. As a result all required TELIS parameters were demonstrated. Phase-locked FFO operation over entire SIR channel frequency range has been realized, spectral resolution below 1 MHz has been confirmed by gas cell and CW signal measurements. An uncorrected double side band (DSB) noise temperature below 250 K has been measured with the phase-locked FFO. The intermediate frequency bandwidth 4-8 GHz has been realized. To ensure remote operation of the phase-locked SIR several procedures for its automatic computer control have been developed and tested.
The superconducting integrated receiver (SIR) comprising in one chip a superconductor-insulator-superconductor (SIS) mixer and a phase-locked superconducting flux flow oscillator (FFO) is under development for the international project TELIS. To overcome temperature constraints and extend operation frequency of the SIR we have developed and studied Nb-AlN-NbN-Nb circuits with a gap voltage Vg up to 3.7 mV and extremely low leakage currents . Based on these junctions integrated microcircuits comprising FFO and harmonic mixer have been designed, fabricated and tested; the radiation from such circuits has been measured at frequencies up to 700 GHz. Employment of NbN electrode does not result in the appearance of additional noise. For example, FFO linewidth as low as 1 MHz was measured at 600 GHz, that allows us to phase lock up to 92% of the emitted by FFO power and realize very low phase noise about 90 dBc. Preliminary results demonstrated uncorrected DSB noise temperature of the Nb-AlN-NbN SIR below 250 K at frequencies around 600 GHz.