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IEEE Transactions on Applied Superconductivity

Timing jitter and bit errors in a 64-bit circular shift register

Andrea M. Herr, M. J. Feldman, Mark F. Bocko

Published Jun 1, 1999• 16 citations
Publisher

Abstract

The bit-error rate of a 64-bit single-flux-quantum circular shift register, operating at a clock frequency of 10-16 GHz was measured. Error incidence depends on the values of the clock and data bias currents and on the clock frequency. Timing violation arising from thermal jitter is the dominant error mechanism. The jitter per JTL stage is estimated to be 290 fs based on the error rate data. This corresponds to a noise temperature of 8-9 K.

DOI
10.1109/77.783836

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IEEE Transactions on Applied Superconductivity•Jun 1, 1999•69 citations
The bit-error rate of a 64-bit single-flux-quantum circular shift register, operating at a clock frequency of 10-16 GHz was measured. Error incidence depends on the values of the clock and data bias currents and on the clock frequency. Timing violation arising from thermal jitter is the dominant error mechanism. The jitter per JTL stage is estimated to be 290 fs based on the error rate data. This corresponds to a noise temperature of 8-9 K.
Timing jitter is an important constraint for the performance of SFQ circuits. We focus on the timing jitter in a Josephson transmission line (JTL) that induces timing errors at logic gates. A proper data analysis of 2-bit shift registers gave a jitter value of about 0.08 ps for a single Josephson junction in a JTL powered at a designed bias current. The variations in timing parameters of logic cells also give rise to timing errors. We experimentally determined the timing parameters in several logic cells and found that the deviations between actual and nominal values are within 2 ps. The relationship between the gray zone and circuit scale was estimated by extrapolating the transition curves observed in 2-bit shift registers. The estimated circuit scale was 20,000-100,000 JJs and 1,000 JJs at an operating clock frequency of 20 GHz and 40 GHz, respectively.
A 64-bit superconducting rapid single flux quantum (RSFQ) circular shift register (CSR) has been demonstrated to operate at clock frequencies up to 18 GHz. The CSR was designed with special attention to timing constraints, which are more severe for "recurrent" circuits (where data must circulate around closed feedback loops) than for systolic arrays where only local timing constraints are relevant. The longest recurrent data path ever demonstrated previously was only several stages long. The testing scheme demonstrated here is unique in that the data circulated up to 50 million times before verification.
Timing jitter is an important factor in determining the limit of speed and scale of single-flux-quantum circuits. We estimated the timing jitter by a simple method using 2-bit shift registers. It was estimated by observing the transition between 1- and 2-mode operations while changing the bias current to the clock line. A sharp transition was observed in the shift register with a smaller number of Josephson junctions in the clock and data lines, suggesting the existence of a finite timing jitter. The timing jitter per Josephson junction was estimated to be 0.09 ps at a designed bias current. The temperature dependence supported that the timing jitter comes from thermal fluctuation.
Error rates of rapid-single-flux-quantum (RSFQ) shift register memories were investigated using a high-speed error-rate measurement system in order to demonstrate their reliability and stability. We designed and implemented an 8 times 8-bit shift register memory using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The total number of Josephson junctions including the test system is 4184, and the circuit area is 2.1 mm times 3.2 mm. We measured the error rates of every storage node by reading out the data 216times at the clock frequency of 16 GHz. The measured error rates were lower than 10-10with DC bias margin better than plusmn5%.
Rapid Single Flux Quantum (RSFQ) logic is well-known for its ultra-high switching speed and extremely low power consumption. In this paper, we present two original experiments to demonstrate that it's also a reliable technology and its reliability is sufficient even for such a large-scale system as a proposed petaflops-scale HTMT computer. We have measured the bit error rate (BER) for a circular register of inverters representing a critical path of a 64-bit integer adder, and timing jitter in a 200 Josephson junction (JJ) long transmission line, imitating a branch of a clock distribution tree, both being important and representative building blocks of the HTMT computer. For the adder critical path we have demonstrated the highest clock frequency of 17 GHz, latency of 860 ps and BER of 10/sup -19/ for 3.5 /spl mu/m technology of HYPRES, Inc. The value of timing jitter was 200 fs per JJ for 1.5 /spl mu/m technology of TRW, Inc. These figures are in good agreement with our simulations.
We have carried out measurements of bit error rate (BER) of Rapid Single-Flux-Quantum (RSFQ) XOR gates with various nominal dc power supply voltages (from 0.1 V to 1.0 mV), operating at speeds up to 25 GHz. (For these gates, implemented using HYPRES' standard, 3.5-/spl mu/m, 10 /spl mu/A//spl mu/m/sup 2/ Nb-trilayer process, this speed is close to maximum.) A special on-chip RSFQ test circuit allowed high-speed measurements of BER in the range from 10/sup -9/ to 10/sup -13/ to be carried out. As a result of these experiments, a new type of thermal-fluctuation-induced digital errors in RSFQ circuits has been identified. These "timing" errors arise at high speed due to time jitter of data and clock pulses. We have developed a simple theory of these errors which allows a fair description of the experimental data. The theory shows that in some cases the timing errors may be an important factor limiting speed performance of RSFQ circuitry. Nevertheless, our XOR gates could operate at 25 GHz with BER below 10/sup -13/ at the standard temperature (4.2 K) at any dc power supply voltage in our range. For the lowest voltage (0.1 Volt) the calculated static power dissipation in the gate was as low as 23 nanowatts, lower than the unavoidable dynamic dissipation (43 nanowatts).