Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Electron Device Letters

Experimental SFQ interferometer shift register prototype with Josephson junctions

W. Jutzi, E. Crocoll, R. Herwig, Henrik Kratz, M. Neuhaus, H. Sadorf, J. Wunsch

Published Mar 1, 1983• 15 citations
Publisher

Abstract

A shift register prototype has been implemented with lead-alloy technology. Single-flux quanta have been shifted in both directions by local magnetic fields with a maximum repetition frequency of 250 MHz. The absence or presence of a flux quantum at a given position is read out nondestructively. The speed and the miniaturisation potential of the proposed shift register is discussed.

DOI
10.1109/edl.1983.25643

Related papers

Performance issues in single flux quantum shift registers

J.H. Hang, John X. Przybysz

Testing on a single-flux-quantum (SFQ) shift register fabricated with a SFQ Nb-AlO/sub x/Nb Josephson junction process indicates that a stable flux quantum can be stored in a rapid SFQ (RSFQ) shift register stage and be shifted by SFQ pulses. Design simulations showed that logic errors can occur in SFQ shift registers even though the circuit passes the average voltage test. Three-junction-per-stage shift registers had an advantage over the two-junction-per-stage shift register in handling data with successive 1's and in incorporating resistors to increase tolerance of trapped magnetic flux. Input and output buffers for data and clock pulses were added to get an RSFQ shift register to obtain correct performance. The highest error-free operation speed for the data with successive 1's is about half of the speed for propagation of a lone data 1. Error-free operation of SFQ shift registers with three junctions per stage could be obtained up to speeds of 30-60 GHz with Josephson junctions having I/sub c/R/sub n/ (critical-current-normal-resistance product) values of 600 mu V.>

IEEE Transactions on Applied Superconductivity•Mar 1, 1993•8 citations

Margins of a 16-ps/bit interferometer shift register

H. Beha, W. Jutzi, G. Mischke

Static and dynamic properties of an interferometer with five equal Josephson junctions are investigated as a single-flux quanta shift-register model. A flux quantum is stored in any loop without a bias current or magnetic field. A flux quantum is shifted from one interferometer loop to the adjacent one by applying a magnetic-field control pulse only to one in terferometer loop at a time. Shift current margins determined statically and dynamically are larger than about ±30 percent; the write current margins are ±25 percent. Within these tolerances, and for a maximum Josephson current density of 10 kA/ cm2, delays of 16 ps/bit, including shift and write, have been simulated.

IEEE Transactions on Electron Devices•Oct 1, 1980•15 citations

A 3 bit single flux quantum shift register based on high-Tc bicrystal Josephson junctions operating at 50 K

B. Oelze, B. Ruck, Erik Sodtke +3 more

A 3 bit single flux quantum (SFQ) shift register based on high-Tc bicrystal Josephson junctions has been designed, fabricated, and experimentally tested. The circuit consists of 26 bicrystal Josephson junctions and includes the shift register itself, two dc-SFQ converters, one readout superconducting quantum interference device, serving as a SFQ-dc converter, and three Josephson transmission lines. The correct operation of all circuit components has been demonstrated by low frequency testing at a temperature of 50 K.

Applied Physics Letters•Feb 3, 1997•22 citations

Design and Testing of Rapid Single Flux Quantum Shift Registers with Magnetically Coupled

Readout Gates, Perng-Fei Yuh, Oleg A. Mukhanov

Experimental superconducting shift registers con- sisting of on-chip clock generators, clock regeneration and dis- tribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic / memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed opera- tion of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AIO,/Nb Josephson-junction process at a critical-current density of 1000 A / cm2. The power dissipation per bit is 3 p.W.

•Jan 1, 1992•0 citations

RSFQ 1024-bit shift register for acquisition memory

Oleg A. Mukhanov

Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of +or-23% and +or-14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO/sub x//Nb process with a junction critical current density of 1.0 kA/cm/sup 2/.>

IEEE Transactions on Applied Superconductivity•Jan 1, 1993•73 citations

Design and testing of rapid single flux quantum shift registers with magnetically coupled readout gates

Perng-Fei Yuh, Oleg A. Mukhanov

Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>

IEEE Transactions on Applied Superconductivity•Jan 1, 1992•21 citations
A shift register prototype has been implemented with lead-alloy technology. Single-flux quanta have been shifted in both directions by local magnetic fields with a maximum repetition frequency of 250 MHz. The absence or presence of a flux quantum at a given position is read out nondestructively. The speed and the miniaturisation potential of the proposed shift register is discussed.
Testing on a single-flux-quantum (SFQ) shift register fabricated with a SFQ Nb-AlO/sub x/Nb Josephson junction process indicates that a stable flux quantum can be stored in a rapid SFQ (RSFQ) shift register stage and be shifted by SFQ pulses. Design simulations showed that logic errors can occur in SFQ shift registers even though the circuit passes the average voltage test. Three-junction-per-stage shift registers had an advantage over the two-junction-per-stage shift register in handling data with successive 1's and in incorporating resistors to increase tolerance of trapped magnetic flux. Input and output buffers for data and clock pulses were added to get an RSFQ shift register to obtain correct performance. The highest error-free operation speed for the data with successive 1's is about half of the speed for propagation of a lone data 1. Error-free operation of SFQ shift registers with three junctions per stage could be obtained up to speeds of 30-60 GHz with Josephson junctions having I/sub c/R/sub n/ (critical-current-normal-resistance product) values of 600 mu V.>
Static and dynamic properties of an interferometer with five equal Josephson junctions are investigated as a single-flux quanta shift-register model. A flux quantum is stored in any loop without a bias current or magnetic field. A flux quantum is shifted from one interferometer loop to the adjacent one by applying a magnetic-field control pulse only to one in terferometer loop at a time. Shift current margins determined statically and dynamically are larger than about ±30 percent; the write current margins are ±25 percent. Within these tolerances, and for a maximum Josephson current density of 10 kA/ cm2, delays of 16 ps/bit, including shift and write, have been simulated.
A 3 bit single flux quantum (SFQ) shift register based on high-Tc bicrystal Josephson junctions has been designed, fabricated, and experimentally tested. The circuit consists of 26 bicrystal Josephson junctions and includes the shift register itself, two dc-SFQ converters, one readout superconducting quantum interference device, serving as a SFQ-dc converter, and three Josephson transmission lines. The correct operation of all circuit components has been demonstrated by low frequency testing at a temperature of 50 K.
Experimental superconducting shift registers con- sisting of on-chip clock generators, clock regeneration and dis- tribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic / memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed opera- tion of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AIO,/Nb Josephson-junction process at a critical-current density of 1000 A / cm2. The power dissipation per bit is 3 p.W.
Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of +or-23% and +or-14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO/sub x//Nb process with a junction critical current density of 1.0 kA/cm/sup 2/.>
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>