This paper presents a sigma delta bandpass ADC modelling based on RSFQ (rapid single flux quantum) technology with VHDL-AMS. A Josephson junction model is proposed and simulated based on RCSJ electrical model. Each ADC element is dissociated and simulated to validate its behaviour. We assimilate ADCpsilas comparator which is composed by two Josehpson junctions to an ideal rectangular pulses generator. Pulses duration is directly a physical parameter obtained by technology. We give relations between ADC performance (SNR) to the comparator SFQ pulses form and duration with normalized physical parameters.
This paper presents a sigma delta bandpass ADC modelling based on RSFQ (rapid single flux quantum) technology with VHDL-AMS. A Josephson junction model is proposed and simulated based on RCSJ electrical model. Each ADC element is dissociated and simulated to validate its behaviour. We assimilate ADCpsilas comparator which is composed by two Josehpson junctions to an ideal rectangular pulses generator. Pulses duration is directly a physical parameter obtained by technology. We give relations between ADC performance (SNR) to the comparator SFQ pulses form and duration with normalized physical parameters.
Successful utilization of the quasi one-junction SQUID (QOS) as a signal comparator for analog-to-digital conversion (ADC) has been demonstrated by several groups, This idea is extended to show how similar comparators can be integrated into an all rapid single flux quantum (RSFQ) digital architecture. Comparators are interrogated by SFQ sampling pulses and in turn give output according to the RSFQ convention. One- and two-bit ADC's have been simulated, fabricated and tested at low speed. Total performance of these devices is estimated within the framework of a multiple bit parallel flash ADC architecture.>
A new generation of the Josephson digital circuits-rapid single flux quantum (RSFQ) devices-based on overdamped externally shunted high quality Nb-AlO x -Nb tunnel junctions have been designed, fabricated and experimentally investigated. All-refractory material 11-layer 5 mu m integrated technology has been successfully employed for the preparation of the RSFQ microcircuits. The T flip-flop has been demonstrated to operate properly up to clock frequencies of 100 GHz at 25% margins. The proper operation of the buffer stage for a one-directional SFQ pulse transmission at clock frequencies up to 125 GHz has been achieved. The possibilities to convert the information from the usual DC form to SFQ and vice versa have been demonstrated. An output signal in an SFQ/DC converter as high as 220 mu V has been measured. A new counter type A/D converter which includes a comparator and reversible binary counter with DC outputs has been fabricated and tested. The proposed ADC seems to be very promising for high-accuracy measurement of medium-bandwidth signals. The possibilities of creating a number of SFQ devices with outstanding parameters are discussed.
Abstract\nThis diploma work is about Rapid Single Flux Quantum (RSFQ) circuits. This\nsupercoducting digital circuitry has the most promising properties in terms of speed and\npower consumption. The active elements of the RSFQ circuits are Josephson junctions (JJ).\nFor their fabrication low temperature superconducting niobium films are used. Today the\ndesign and fabrication of RSFQ circuits are done in a standardized way with well-defined\ndesign rules. Nevertheless, to design complicated circuits with more than several hundred\njunctions a lot of practical problems must be solved.\nDifferent aspects of the RSFQ circuits design process were investigated in this work.\nIn the theoretical part we propose a new, more realistic model of the Josephson junction for\nphysical simulation (which is necessarily used for design of every RSFQ gate) in order to\nimprove its quality and precision. The new model for the JJ includes additional inductances,\nwhich must reflect a specific environment of the junction layout. The influence of parameter\ndeviations was investigated in the simulation. As sources of the deviation we chose the\nspread of c (the Stewart-McCumber parameter) and that of the inductances. Then the\noperational margins of the basic elements of the RSFQ logic SR flip-flop were determined\nand compared with the prediction of the previously used model. To prove the results of\nsimulations we designed a test structure of the SR flip-flop, with c=1 and c=2 for the wellestablished\nHYPRES technology (USA).\nAnother part of the work is practical measurements. A test chip, containing chains of 100\nJosephson junctions was designed and measured in order to estimate the spread of critical\ncurrents in real technology.
Software-Defined Radio (SDR), as explained in [1], is a promising concept for the wireless communication industry since the entire transceiver function can be implemented in software, avoiding the replacement of hardware each time the system has to be upgraded. However, the practical implementation of such a system is depended on the hardware, which consists of precise, ultra highspeed electronic devices such as Analog-to-Digital Converters (ADCs). The present state-of-the-art semiconductor ADCs cannot be used for the implementation of SDR in the near future [2]. Some of the factors that hamper the implementation are the requirements of very high speed of a few tens of GHz and the high resolution (e.g. 16 bits) at these speeds. On the other hand, using the Low-Temperature Superconducting (LTS) technology [3], which relays on the quantum mechanical property of superconductors, very high-speed electronic devices with the accuracy of a flux quantum, can be constructed. In a closed superconducting loop, the magnetic flux can exist only in discrete quantized amounts equal to the multiples of the magnetic flux quantum, φ0 = h/2e ~ 2.07x10 Wb. The theoretical speed limit of such a Rapid Single Flux Quantum (RSFQ) device is close to 1 THz [4]. These RSFQ circuits are the fastest of all devices built in any known technology. The basic building block of an RSFQ circuit is the Josephson Junction (JJ), which is formed when two superconductors are separated by an interface. Since RSFQ circuits work at extremely high speeds, testing and verification of such a device is a difficult and challenging task. Direct testing at these speeds is not possible at this moment. Furthermore, the costs of the equipment required for such tests would be extremely high. Hence methods have to be developed to reduce the requirements of external
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
A new family of dc-powered Josephson junction digital devices, the Rapid Single Flux Quantum (RSFQ) logic, is described. The devices use overdamped Josephson junctions and two-junction interferometers to store, pass and process the digital information presented in form of single flux quanta. We have carried out extensive numerical simulation of the dynamics of the RSFQ logic gates and of some more complex circuits including serial full adder and reversible shift register, within the standard microscopic-theory ("Werthamer") description of Josephson junctions. The minimum clock cycles of the basic RSFQ circuits turn out to be as small as 2.5 ps. The most promising ways to use the RSFQ logic circuits at the present stage of development of the Josephson junction digital technology are discussed.