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Electronics and Communications in Japan (Part II Electronics)

Fabrication of NbN single flux quantum (SFQ) circuit and operating properties at 10 K

Hirotaka Terai, Zhen Wang

Published Sep 18, 2001• 4 citations
Publisher

Abstract

Abstract We fabricated a prototype of a single flux quantum (SFQ) logic circuit for operation near 10 K by using NbN, which has a critical temperature around 16 K. This circuit is fabricated on a 2‐inch silicon (Si) substrate based on the NbN/AlN/NbN tunnel junction having fluctuations in the critical current of ±5% or less from 976 Josephson junctions (JJ). The fabrication of a prototype circuit to generate, propagate, and detect SFQ pulses and the examination of its operation confirmed normal operation up to approximately 9.8 K, which is close to 10 K. In addition, at the operating temperature of 8.5 K, the operations of elementary cells such as a confluence buffer and a T flip‐flop were verified and were successful in the operation of the largest scale circuit, an 8‐bit shift register consisting of 105 JJ. © 2001 Scripta Technica, Electron Comm Jpn Pt 2, 84(10): 34–39, 2001

DOI
10.1002/ecjb.1063

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IEEE Transactions on Applied Superconductivity•Dec 1, 2005•16 citations
Abstract We fabricated a prototype of a single flux quantum (SFQ) logic circuit for operation near 10 K by using NbN, which has a critical temperature around 16 K. This circuit is fabricated on a 2‐inch silicon (Si) substrate based on the NbN/AlN/NbN tunnel junction having fluctuations in the critical current of ±5% or less from 976 Josephson junctions (JJ). The fabrication of a prototype circuit to generate, propagate, and detect SFQ pulses and the examination of its operation confirmed normal operation up to approximately 9.8 K, which is close to 10 K. In addition, at the operating temperature of 8.5 K, the operations of elementary cells such as a confluence buffer and a T flip‐flop were verified and were successful in the operation of the largest scale circuit, an 8‐bit shift register consisting of 105 JJ. © 2001 Scripta Technica, Electron Comm Jpn Pt 2, 84(10): 34–39, 2001
We report on the fabrication and the operation of all-NbN rapid single flux quantum (RSFQ) circuits. The NbN integrated circuit consists of NbN/AlN/NbN tunnel junctions, Mo resistors, sputtered SiO/sub 2/ insulating layers, and 400-nm-thick NbN ground plane and wiring layer. The circuits were fabricated with the minimum junction size of 2 /spl mu/m/spl times/2 /spl mu/m and the alignment margin of +/-0.5 /spl mu/m. We designed RSFQ logic cells under critical current density of 2.5 kA/cm/sup 2/, sheet resistance of 2 /spl Omega/ and sheet inductance of 1.4 pH. We experimentally investigated dc bias margin of the fabricated RSFQ cells at 9 K. We observed relatively large dc bias margin of more than +/-25% for a pulse splitter, a confluence buffer and an RS flip-flop, while the dc bias margin of a T flip-flop was less than +/-5%. We succeeded to demonstrate the operation of 16-bit concurrent flow shift register at 9 K.
Abstract We report on the electrical properties of NbN/TaN/NbN Josephson junctions grown on thermally oxidized silicon substrates, along with the design and fabrication of superconducting single-flux-quantum (SFQ) circuits based on these NbN superconductor/normal metal/superconductor (SNS) junctions. The critical current density ( J c ) of the junctions was found to be relatively sensitive to the barrier thickness, decreasing from 108.0 ± 8.1 kA cm −2 for a 15 nm barrier to 12.8 ± 1.9 kA cm −2 for a 30 nm barrier. For a J c of approximately 24.5 ± 2.1 kA cm −2 and a barrier thickness of 25 nm, the NbN SNS junctions are self-shunted and exhibit nonhysteretic current–voltage ( I – V ) characteristics. Especially for junctions with diameter ( φ ) ranging from 0.8 to 1.6 μ m, their critical current ( I c ) falls within the range of 110–450 μ A, making them suitable for SFQ circuits. By considering the impact of excess current and incorporating it as an additional term in the conventional resistively and capacitively shunted junction model, the I – V curves of NbN SNS junctions can be precisely described, successfully minimizing the deviation between simulations and test results. The DC-SFQ and SFQ-DC interface circuits can both operate normally, and the bias margins of cell circuits such as Josephson transmission line, confluence buffer, D flip-flop, and splitter are greater than 40%. Compared to Nb superconductor/insulator/superconductor junctions, their self-shunting characteristics and relatively thick 25 nm barriers can also enhance the integration of circuits and increase the yield to complex circuits.
We have developed an all-NbN integrated circuit technology for future integration of single flux quantum (SFQ) circuit with superconducting single-photon detector array. The all-NbN integrated circuits consist of epitaxial NbN/AlN/NbN tunnel junctions fabricated on single-crystal MgO substrates, Mo shunt resistors and 500-nm-thick NbN ground plane on the top. Critical current density and sheet resistance of the Mo resistor were set at 2.5 kA/cm2and 1.2 Ω, respectively. Current uniformity of the NbN/AlN/NbN tunnel junctions was measured to be σ = 3% for 3 μm × 3 μm junction size. The NbN-based SFQ logic cells were designed for and tested at 4.2 K. We actually measured circuit inductances of the fabricated SFQ cells. Circuit simulation revealed that the measured circuit inductances in the fabricated SFQ cells should allow operating margins of more than +/-20%.
This paper presents a study on the merits of single flux quantum (SFQ) logic in superconducting digital electronics. With no requirements for an external RF clock source, the speed of SFQ logic circuits can exceed 100 GHz, orders of magnitude higher than latching logic circuits. Use of overdamped junctions in SFQ circuits makes this logic available for already developed high-Tc junctions. Simulations show the operation of SFQ circuits at above 10 GHz with the junctions having characteristics similar to those of YBa2Cu3O7-x/Au/YBa2Cu3O7-x planar junctions. A similar concept is applied to NbN circuits operable above 10 K. A flip-flop counter using NbN junctions with Vm (1.5 mV)=3 mV and Delta =1.9 mV to model 12 K operation has been successfully simulated up to 5 GHz. Operating margins of only 26% on MVTL shift register were obtained by simulations, which is comparable to the margins for SFQ logic circuits. A counting SFQ analogue-to-digital converter can be improved by using an output buffered quantizer.
We have developed resistively shunted NbN junctions to realize superconducting single flux quantum circuits operating at 10 K and/or high speed. The junctions consist of epitaxial NbN/AlN/NbN tunnel junctions and molybdenum (Mo) resistors fabricated on single-crystal MgO substrates. The junction qualities are systematically investigated in a wide range of critical current density (Jc). The gap voltage and the ratio of Rsg/RN were about 5.6 mV and 11 for the junctions with the Jc of 10 kA/cm2, respectively. The overdamped Josephson junctions with parallel Mo resistors having a nominal sheet resistance showed non-hysteretic current-voltage characteristics for the junctions with Jc of 10 kA/cm2.
Single flux quantum (SFQ) circuit components such as an SFQ-dc converter and a confluence buffer have been fabricated by using an YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// ramp-edge junction technology and their logic operations at temperatures up to near 60 K were investigated. The SFQ-dc converter was correctly operated in a wide temperature range from 4.2 K to 56 K and found to be useful for detecting output signals from other SFQ circuit components at any operating temperatures. The basic function that a signal from either of two input Josephson transmission lines (JTLs) was transmitted to an output JTL was confirmed for the confluence buffer and finite operating margins were obtained at temperatures from 42 K to 61 K. The narrowest margin of dc supply current obtained at temperatures from 55 K to 60 K was /spl plusmn/20% and was consistent with the simulation. Margin reduction due to thermal noise was also evaluated. According to the analytical calculation, the operating margin to keep the bit-error rate less than 10/sup -5/ was as large as /spl plusmn/20% even at 50 K when the value of junction critical-current I/sub c/ was kept near 0.4 mA.