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IEEE Transactions on Applied Superconductivity

Recent Progress in SFQ Device Technologies in Japan

K. Tanabe, M. Hidaka

Published Jun 1, 2007• 11 citations
Publisher

Abstract

Recent progress in single flux quantum (SFQ) device technologies in Japan is described, mainly focusing on those developed in the NEDO "Superconductors Network Device Project" which includes developments of both LTS and HTS devices. The advanced Nb process which consists of a planarized structure with nine Nb layers and 10 kA/cm2Josephson junctions (JJs) has been developed. This enables fabrication of chips including 100,000 JJs and operating frequency up to 80 GHz. We have also developed the CAD tool by which one can generate SFQ circuit layouts including about 400,000 JJs from logic descriptions. For demonstration of a small-scale switch system, a 4 times 4 switch chip, a 117 Gbps multi-chip-module (MCM) technology, and a packaging technology with 32-ch 10 Gbps I/Os to an MCM have been developed. By using the multilayer process with three HTS epitaxial layers and interface-engineered ramp-edge JJs, we demonstrated operation of SFQ circuits with up to 200 JJs. A variety of elementary SFQ circuits such as a T-FF and a 1:2 switch required for an A/D converter front-end circuit have been designed based on a new layout method, and their operation at 30-50 K has been confirmed. A prototype sampler system is being developed for demonstration of bandwidth over 100 GHz for optical input signals.

DOI
10.1109/tasc.2007.898704

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Recent progress in single flux quantum (SFQ) device technologies in Japan is described, mainly focusing on those developed in the NEDO "Superconductors Network Device Project" which includes developments of both LTS and HTS devices. The advanced Nb process which consists of a planarized structure with nine Nb layers and 10 kA/cm2Josephson junctions (JJs) has been developed. This enables fabrication of chips including 100,000 JJs and operating frequency up to 80 GHz. We have also developed the CAD tool by which one can generate SFQ circuit layouts including about 400,000 JJs from logic descriptions. For demonstration of a small-scale switch system, a 4 times 4 switch chip, a 117 Gbps multi-chip-module (MCM) technology, and a packaging technology with 32-ch 10 Gbps I/Os to an MCM have been developed. By using the multilayer process with three HTS epitaxial layers and interface-engineered ramp-edge JJs, we demonstrated operation of SFQ circuits with up to 200 JJs. A variety of elementary SFQ circuits such as a T-FF and a 1:2 switch required for an A/D converter front-end circuit have been designed based on a new layout method, and their operation at 30-50 K has been confirmed. A prototype sampler system is being developed for demonstration of bandwidth over 100 GHz for optical input signals.
The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.
We have developed the fabrication process, the circuit design technology, and the cryopackaging technology for high-Tc single flux quantum (SFQ) devices with the aim of application to an analog-to-digital (A/D) converter circuit for future wireless communication and a sampler system for high-speed measurements. Reproducibility of fabricating rampedge Josephson junctions with IcRn products above 1mV at 40K and small Ic spreads on a superconducting groundplane was much improved by employing smooth multilayer structures and optimizing the junction fabrication process. The separated base-electrode layout (SBL) method that suppresses the Jc spread for interface-modified junctions in circuits was developed. This method enabled low-frequency logic operations of various elementary SFQ circuits with relatively wide bias current margins and operation of a toggle-flip-flop (T-FF) above 200GHz at 40K. Operation of a 1:2 demultiplexer, one of main elements of a hybrid-type Σ-Δ A/D converter circuit, was also demonstrated. We developed a sampler system in which a sampler circuit with a potential bandwidth over 100GHz was cooled by a compact stirling cooler, and waveform observation experiments confirmed the actual system bandwidth well over 50GHz.
Superconducting devices have intrinsically superior characteristics to those of semiconductor devices. Presently, we can fabricate more than twenty thousand junctions on one chip using niobium technology. We have demonstrated the operation of a network system with a superconducting interconnection chip using voltage-state logic. Single flux quantum devices are promising for future superconducting applications because the clock frequency of SFQ logic is higher than that of voltage-state. We have proposed a high-end switch based on hybrid architecture using optical devices, semiconductors and SFQ devices. To demonstrate the high-speed operation of SFQ circuits, we developed an arbiter circuit that uses SFQ components and the arbiter circuit operates at 60 GHz. We also have developed a high Tc superconducting (HTS) SFQ sampler system for observing ultra-fast signal waveforms. In addition, we will discuss the prospects of future superconducting devices based on the fabrication technologies we developed.
I describe the fundamental technologies concerning the single flux quantum (SFQ) logic circuits. Recent remarkable progress in the computer-aided-design (CAD) tool, which is based on the cell-based design technique, enables us to make SFQ integrated circuits. Although the circuit demonstrated so far has 2, 300 Josephson junctions at most, this number will increase because the CAD tool is advancing. The on-chip test system has also been developed to test the high-speed nature of the SFQ circuit. For example, the shift-register employed as a circuit under test operates correctly at 55GHz. I also describe the potential applications of the SFQ circuits. An analog-to-digital converter utilizing the high-speed nature and high sensitivity in the SFQ circuits will be applicable to the front end of the future base stations, which require broad band width, high sensitivity, and flexibility. Packet switches used in the future high-end router need high throughput and functionality. Only SFQ-based packet switches can meet these requirements. Another potential application is a high-end server. We have studied micro-architectures of a processor executing the Java Byte Codes directly and a multiprocessor system constructed by connecting the processors and memories via the ultra-broad-band SFQ network switches. Throughout the study, we employ the concept of the complexity-reduction (CORE), in which the high-speed nature of the SFQ circuits is used for the reduction of the circuit scale or simplification of the micro-architecture; the multiprocessor system has high performances. These clear applications promote rapid technological progress in the SFQ technology, though we must make every endeavor to find new application fields.
Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.
We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 1×1μm, a line width of 0.8μm, a JJ critical current density of 10kA/cm2, a 2.4Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.