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IEEE Transactions on Applied Superconductivity

High speed testing of a four-bit RSFQ decimation digital filter

Quentin Herr, Kris Gaj, Andrea M. Herr, Nada Vukovic, C.A. Mancini, Mark F. Bocko, M. J. Feldman

Published Jun 1, 1997• 25 citations
Publisher

Abstract

We have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high speed test requires only a low speed interface and standard low-cost measurement equipment. Three auxiliary test units built of simple RSFQ circuits are used. A circular JTL structure generates an on-chip high speed clock with frequency adjustable from 4 to 16 GHz. A pseudo-random number generator with period 64 clock cycles provides parallel input to the filter. Finally, 12 four-bit acquisition shift registers collect output data. We have integrated all the above units on a single chip. The chip is initialized at low speed, run at high speed, and read out at low speed. Our testing scheme is superior to previously reported high-speed tests in the area of the added circuitry, in the requirements on high-speed input/output, in control, and in the parameters of the measurement equipment. The scheme can be easily adapted to test various RSFQ circuits.

DOI
10.1109/77.621942

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We have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high speed test requires only a low speed interface and standard low-cost measurement equipment. Three auxiliary test units built of simple RSFQ circuits are used. A circular JTL structure generates an on-chip high speed clock with frequency adjustable from 4 to 16 GHz. A pseudo-random number generator with period 64 clock cycles provides parallel input to the filter. Finally, 12 four-bit acquisition shift registers collect output data. We have integrated all the above units on a single chip. The chip is initialized at low speed, run at high speed, and read out at low speed. Our testing scheme is superior to previously reported high-speed tests in the area of the added circuitry, in the requirements on high-speed input/output, in control, and in the parameters of the measurement equipment. The scheme can be easily adapted to test various RSFQ circuits.
We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date.
Abstract An on-chip high-frequency testing method for rapid single flux quantum circuits is proposed. This method employs test vectors based on pseudo-random sequences created by an on-chip high-frequency clock generator (CG) and a linear feedback shift register with parallel outputs (LSPO). Downsamplers (DSMs) at the outputs of a circuit under test (CUT) decimate the CUT output data so that high-frequency testing can be performed at sufficiently low data rates between the CUT and room-temperature electronics. The proposed testing can continuously test the circuit at high frequency with low-cost instruments. All of the critical subsystems, including LSPO, CG, and DSM, were designed, fabricated, and successfully tested. We validated proper operation at up to 40 GHz, confirming the concept and execution.
We present the results of low- and high-speed testing of a fully integrated all-digital one-bit RSFQ autocorrelator for short-millimeter and submillimeter wave spectrometry applications. The 16-channel device, complete with a 16/spl times/9 array of binary counters, on-chip double-oversampling quantizer and on-chip clock was operational at clock speeds of up to 11 GHz. The total number of Josephson junctions in the design was 1672, while the estimated total power dissipation was less than 0.1 mW. For high-speed testing of the device we have developed a specialized 16-channel room-temperature interface capable of real-time data acquisition at a 16 Mbps-per-channel output rate. Extensive high-speed on-chip testing of the autocorrelator has also been performed, both in analog and digital modes, in the latter mode with an additional on-chip clock controller. All chips were fabricated in HYPRES' standard 3.5 /spl mu/m-10 /spl mu/A//spl mu/m/sup 2/ Nb-trilayer process. We also present a new concept of a 128-channel autocorrelator system built on 8 independent identical chips with approximately 2,500 Josephson junctions per chip, i.e. within the reach of the present-day fabrication technology.
We have experimentally demonstrated high-speed operation of RSFQ circuits using on-chip testing system and confirmed normal operation up to 30 GHz. The system includes high-frequency pulse generators and shift registers (SRs) serving as an interface circuit between high-speed internal signals and low-speed external signals. We adopted two ladder-type pulse generators. One generates clock pulses of 10 GHz and the other generates 25 GHz. By increasing bias currents of JTLs, clock pulses can be generated at higher frequency. By using the system, an SR and a T flip-flop (TFF) gate are examined. The circuits were fabricated by NEC's standard process based on Nb/AlO x /Nb junction technology with J c = 2.5 kA cm -2 . We optimized circuit parameters by using Monte Carlo simulation. In addition, the effect of parasitic inductances can be reduced by decreasing I c . As a result, the systems for SR and TFF worked correctly up to 30 GHz and 27.5 GHz, respectively. The SR and TFF have wide bias margins of ±39% and ±20%, respectively. We confirmed that the bias margins of the SR are independent of operation frequency. The limits of operation frequency are thought to be much higher than 30 GHz.
We have developed an advanced version of on-chip test system with new high-speed clock generation and control. For high-speed clock generation, a novel wide-bandwidth ring generator is designed using circular Josephson transmission lines with an inductively coupled trigger. The generator is capable of producing SFQ clock pulses in the range of from 15 to 55 GHz using a 1 kA/cm/sup 2/ Nb fabrication process. For clock control, we have designed two different types of clock-controller circuits based on programmable shift-register and counter. Using the on-chip test system, we have successfully tested a parallel multiplier module up to 15 GHz with 16% dc bias margins.
Simple RSFQ gates can be very robust, and operate up to high clock speeds in simulation. Larger RSFQ circuits are generally much more limited in clock speed. We believe that this is partly due to less than optimal choice of the timing inter-connections between gates. Timing design is especially problematic for circuits including data loops (feedback). We have developed a new technique for timing design of RSFQ data loops which may be called "balanced skew clock scheduling." It involves equalizing the minimum clock period between every pair of gates. Mathematical analysis proves the optimality of this scheme and reveals the global timing constraints unique to RSFQ data loops. We used this technique for the design of a simple useful clocked RSFQ circuit, a four-bit pseudo-random number generator (PRNG). Constructed from our standard library cells for a 3.5 /spl mu/m 1000 A/cm/sup 2/ Nb-trilayer process, the PRNG worked up to 50 GHz in Jspice simulation.