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IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)

Ordering techniques for ESOP-based Toffoli cascade generation

Jacqueline E. Rice, Noor Muhammed Nayeem

Published Aug 1, 2011• 20 citations
Publisher

Abstract

This paper describes three techniques for ordering ESOP cubes prior to generation of a Toffoli gate generation. Two of these techniques are from earlier work, while the third is a new approach. The new approach applies rules to manipulate the cubes followed by a reordering process. Our experiments demonstrate that the new approach is much more effective than either of the two previous approaches. We apply template matching as a post-processing step, which results in even further reductions in the number of Toffoli gates.

DOI
10.1109/pacrim.2011.6032905

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This paper describes three techniques for ordering ESOP cubes prior to generation of a Toffoli gate generation. Two of these techniques are from earlier work, while the third is a new approach. The new approach applies rules to manipulate the cubes followed by a reordering process. Our experiments demonstrate that the new approach is much more effective than either of the two previous approaches. We apply template matching as a post-processing step, which results in even further reductions in the number of Toffoli gates.
In this paper a new heuristic ESOP-based synthesis method for Toffoli networks is proposed. This synthesis method takes advantage of the shared-ESOP cubes among the outputs to generate a cascade of Toffoli gates. The method is suitable to generate circuits for functions with large number of input variables. A greedy approach is utilized to select pairs among the different outputs with common ESOP-cubes. The shared terms need only to be realized once and the result can then be transferred to the second output, and thus reducing the number of Toffoli gates. The synthesis algorithm has been applied to a set of benchmark functions. Experimental results show that the algorithm can generate circuits with reduced quantum cost for virtually all functions. Template applications can further improve the results.
In this paper a new Toffoli gate cascade synthesis method is presented. This method is based on previous work and generates a cascade of inverted-control-Toffoli gates from the ESOP representation of a multi-output function. The algorithm first generates a circuit with n + m lines, where n and m are the number of inputs and outputs, respectively. A set of gate transformations are applied to the circuits to remove some of the output lines. The improvements of this new algorithm are twofold: most NOT gates are eliminated and the number of lines is reduced. A significant reduction is the quantum cost of the resulting networks can be observed.
Reversible logic is being suggested as a possibility for overcoming potential power loss and heat dissipation problems that the computing industry may soon be at a loss to overcome. However, for reversible logic to be a solution we must have techniques for synthesizing function descriptions to reversible circuits. This paper presents an improved ESOP-based reversible logic synthesis approach which leverages situations where cubes are shared by multiple outputs and ensures that the implementation of each cube requires just one Toffoli gate. It has the potential to minimize both gate count and quantum cost, and in fact our experimental results show that this technique can reduce the quantum cost up to 75% compared to results from the existing work.
Reversible logic functions can be realized as networks of Toffoli gates. The synthesis of Toffoli networks can be divided into two steps. First, find a network that realizes the desired function. Second, transform the network such that it uses fewer gates, while realizing the same function. This paper addresses the above synthesis approach. We present a basic method and, based on that, a bidirectional synthesis algorithm which produces a network of Toffoli gates realizing a given reversible specification. An asymptotically optimal modification of the basic synthesis algorithm employing generalized mEXOR gates is also presented. Transformations are then applied using template matching. The basis for a template is a network of gates that realizes the identity function. If a sequence of gates in the synthesized network matches a sequence comprised of more than half the gates in a template, then a transformation using the remaining gates in the template can be applied resulting in a reduction in the gate count for the synthesized network. All templates with up to six gates are described in this paper. Experimental results including an exhaustive examination of all 3-variable reversible functions and a collection of benchmark problems are presented. The paper concludes with suggestions for further research.