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IEEE International Symposium on Multiple-Valued Logic (ISMVL)

ESOP-Based Toffoli Network Generation with Transformations

Yasaman Sanaee, Gerhard W. Dueck

Published Jan 1, 2010• 28 citations
Publisher

Abstract

In this paper a new Toffoli gate cascade synthesis method is presented. This method is based on previous work and generates a cascade of inverted-control-Toffoli gates from the ESOP representation of a multi-output function. The algorithm first generates a circuit with n + m lines, where n and m are the number of inputs and outputs, respectively. A set of gate transformations are applied to the circuits to remove some of the output lines. The improvements of this new algorithm are twofold: most NOT gates are eliminated and the number of lines is reduced. A significant reduction is the quantum cost of the resulting networks can be observed.

DOI
10.1109/ismvl.2010.58

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In this paper a new Toffoli gate cascade synthesis method is presented. This method is based on previous work and generates a cascade of inverted-control-Toffoli gates from the ESOP representation of a multi-output function. The algorithm first generates a circuit with n + m lines, where n and m are the number of inputs and outputs, respectively. A set of gate transformations are applied to the circuits to remove some of the output lines. The improvements of this new algorithm are twofold: most NOT gates are eliminated and the number of lines is reduced. A significant reduction is the quantum cost of the resulting networks can be observed.
In this paper a new heuristic ESOP-based synthesis method for Toffoli networks is proposed. This synthesis method takes advantage of the shared-ESOP cubes among the outputs to generate a cascade of Toffoli gates. The method is suitable to generate circuits for functions with large number of input variables. A greedy approach is utilized to select pairs among the different outputs with common ESOP-cubes. The shared terms need only to be realized once and the result can then be transferred to the second output, and thus reducing the number of Toffoli gates. The synthesis algorithm has been applied to a set of benchmark functions. Experimental results show that the algorithm can generate circuits with reduced quantum cost for virtually all functions. Template applications can further improve the results.
A reversible logic function maps each of the 2m input patterns to a unique output pattern. The network cascade structure problem is to realize a reversible function by a cascade of primitive reversible gates. We present a method that synthesizes a network with family of Toffoli gates. The cascade algorithm finds cascade of Toffoli gates with no backtracking and minimal look-ahead, and apply transformations that reduce the number of gates in the network. We have synthesized all three input and output reversible functions and compare our results to the other optimal results. We also present the results of applying our synthesis method to obtain networks for number of benchmark function.
This paper introduces new algorithms to synthesize reversible functions using EXOR-sum of Products-of-EXOR-sums (EPOE) structures. The motivation for using these structures is to reduce the number of as well as the sizes of multiple controlled Toffoli gates, and thus the quantum cost. To achieve these reductions the paper generalizes from existing 2-level AND-EXOR structures (ESOP) commonly used in reversible logic to a mixture of 3-level EXOR-AND-EXOR structures and ESOPs. Our approach can be applied to reversible and permutative quantum circuits to synthesize single output functions on to an output line, with no additional ancilla bits. A comparison of the ESOP minimizer EXORCISM-4 and two variants of the EPOE minimizer, called EPOEM-1s and EPOEM-2, is presented. The results show that EPOE circuits do in fact achieve the above-stated cost reductions, in particular when expressed in terms of Maslov's quantum cost, the metric commonly used in quantum circuit synthesis.
In this paper a synthesis algorithm for reversible ternary logic cascades is presented. The algorithm can find a solution for any reversible ternary function with n inputs and n outputs utilizing ternary inverter gates and the new (quantum realizable) UCTG gates which are a powerful generalization of ternary Toffoli gates and Generalized Ternary Gates [4]. The algorithm is an extension of the algorithm presented by Dueck, Maslov, and Miller in [3]. A unique feature of this algorithm is that it utilizes no extra wires to generate the outputs. A basic compaction algorithm is defined to improve the results of the basic algorithm. This paper also provides the groundwork for transforming any n*n Toffoli based binary synthesis algorithm into a ternary synthesis algorithm using the new UCTG gates.