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IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)

ESOP-based Toffoli Gate Cascade Generation

Kenneth Fazel, Mitchell Aaron Thornton, Jacqueline E. Rice

Published Aug 1, 2007• 191 citations
Publisher

Abstract

An ESOP-based Toffoli gate cascade synthesis algorithm is presented. The algorithm is capable of generating a cascade of reversible gates for logic functions with large numbers of qubits. The algorithm is fast as it uses a simple cost metric heuristic during a recursive divide-and-conquer function to determine NOT and Toffoli gate placement.

DOI
10.1109/pacrim.2007.4313212

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An ESOP-based Toffoli gate cascade synthesis algorithm is presented. The algorithm is capable of generating a cascade of reversible gates for logic functions with large numbers of qubits. The algorithm is fast as it uses a simple cost metric heuristic during a recursive divide-and-conquer function to determine NOT and Toffoli gate placement.
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In this paper a new heuristic ESOP-based synthesis method for Toffoli networks is proposed. This synthesis method takes advantage of the shared-ESOP cubes among the outputs to generate a cascade of Toffoli gates. The method is suitable to generate circuits for functions with large number of input variables. A greedy approach is utilized to select pairs among the different outputs with common ESOP-cubes. The shared terms need only to be realized once and the result can then be transferred to the second output, and thus reducing the number of Toffoli gates. The synthesis algorithm has been applied to a set of benchmark functions. Experimental results show that the algorithm can generate circuits with reduced quantum cost for virtually all functions. Template applications can further improve the results.
Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors present an algorithm and tool for the synthesis of reversible functions. The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates. At each stage, candidate factors, which represent subexpressions common between the Reed-Muller expansions of multiple outputs, are explored in the order of their attractiveness. The algorithm utilizes a priority-based search tree, and heuristics are used to rapidly prune the search space. The synthesis algorithm currently targets the generalized n-bit Toffoli gate library. However, other algorithms exist that can convert an n-bit Toffoli gate into a cascade of smaller Toffoli gates. Experimental results indicate that the authors' algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite. The authors also present results for some benchmark functions widely discussed in literature and some new benchmarks that the authors have developed. The algorithm is shown to synthesize many, but not all, randomly generated reversible functions of as many as 16 variables with a maximum gate count of 25
Reversible logic is being suggested as a possibility for overcoming potential power loss and heat dissipation problems that the computing industry may soon be at a loss to overcome. However, for reversible logic to be a solution we must have techniques for synthesizing function descriptions to reversible circuits. This paper presents an improved ESOP-based reversible logic synthesis approach which leverages situations where cubes are shared by multiple outputs and ensures that the implementation of each cube requires just one Toffoli gate. It has the potential to minimize both gate count and quantum cost, and in fact our experimental results show that this technique can reduce the quantum cost up to 75% compared to results from the existing work.
Compact synthesis results for reversible logic is of major interest in low-power design and quantum computing. Such reversible functions are realized as a cascade of Toffoli gates. In this paper, we present the first exact synthesis algorithm for reversible functions using generalized Toffoli gates. Our iterative algorithm formulates the synthesis problem with d Toffoli gates as a sequence of Boolean Satisfiability (SAT) instances. Such an instance is satisfiable iff there exists a network representation with d gates. Thus we can guarantee minimality. For a set of benchmarks experimental results are given.