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IEEE Journal of Solid-State Circuits

High-temperature superconducting shift registers operating at up to 100 GHz

J. Martens, A. Pance, K. Char, Marie E. Johansson, Stephen R. Whiteley, J. R. Wendt, VINCENT M. HIETALA, Thomas A. Plut, Carol I. H. Ashby, S.Y. Hou, Julia M. Phillips

Published Jan 1, 1994• 7 citations
Publisher

Abstract

Shift registers have been demonstrated in YBaCuO operating at 77 K using from 64 to over 1000 junctions. These are some of the larger scale integrated circuits demonstrated to date using YBaCuO Josephson technology. The circuit is a modified rapid single flux quantum design in which a single trigger pulse causes a one bit shift of the entire word of 32-512 b in length. Two different junction technologies, electron-beam defined nanobridges and epitaxial edge junctions, have been used with parameter spreads ranging from 11% to 22%. Correct operation has been verified with low speed random word tests and circulating data tests while pseudo random bit sequence demonstrations are underway. A practical amount of time to shift between cells has been measured to be about 10 ps.>

DOI
10.1109/4.272094

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IEEE Transactions on Applied Superconductivity•Mar 1, 1993•79 citations
Shift registers have been demonstrated in YBaCuO operating at 77 K using from 64 to over 1000 junctions. These are some of the larger scale integrated circuits demonstrated to date using YBaCuO Josephson technology. The circuit is a modified rapid single flux quantum design in which a single trigger pulse causes a one bit shift of the entire word of 32-512 b in length. Two different junction technologies, electron-beam defined nanobridges and epitaxial edge junctions, have been used with parameter spreads ranging from 11% to 22%. Correct operation has been verified with low speed random word tests and circulating data tests while pseudo random bit sequence demonstrations are underway. A practical amount of time to shift between cells has been measured to be about 10 ps.>
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>
Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of +or-23% and +or-14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO/sub x//Nb process with a junction critical current density of 1.0 kA/cm/sup 2/.>
Experimental superconducting shift registers con- sisting of on-chip clock generators, clock regeneration and dis- tribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic / memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed opera- tion of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AIO,/Nb Josephson-junction process at a critical-current density of 1000 A / cm2. The power dissipation per bit is 3 p.W.
Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm −2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters β c of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.
A 3 bit single flux quantum (SFQ) shift register based on high-Tc bicrystal Josephson junctions has been designed, fabricated, and experimentally tested. The circuit consists of 26 bicrystal Josephson junctions and includes the shift register itself, two dc-SFQ converters, one readout superconducting quantum interference device, serving as a SFQ-dc converter, and three Josephson transmission lines. The correct operation of all circuit components has been demonstrated by low frequency testing at a temperature of 50 K.
The author presents the design and test results for a novel, buffered RSFQ shift register. The register design makes it possible to build a circular 64-b shift register which is insensitive to the clock pulse direction within the experimentally measured DC bias margin of +or-15%. The implementation of a large variety of unidirectional shift registers using either a buffered or a two-Josephson-junction cell design confirms an expected wide DC bias margin of +or-30% (for a 32-b) and high speed, up to 60 GHz (for a 4-b register). Among these circuits is a 256-b shift register. To the author's knowledge, this is the largest RSFQ circuit (533 junctions) reported to date. This shift register was tested to have a DC bias margin of +or-6% and proper high-speed operation up to 12 GHz.>