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IEEE Transactions on Applied Superconductivity

A Quantum-Accurate Two-Loop Data Converter

Quentin Herr, Donald L. Miller, Aaron A. Pesetski, John X. Przybysz

Published Jun 1, 2009• 6 citations
Publisher

Abstract

High performance oversampling delta-sigma data converters require high clock rates and accurate feedback of the digital output to the analog regime. Superconductor modulators offer the unique advantages of clock rates in the tens-of-gigahertz, comparator switching energy below attoJoules, and quantum-accurate digital-to-analog feedback. We have designed a two-loop baseband modulator whose noise transfer function was calculated using a simple, linear circuit model. The circuit was fabricated in a commercial superconductor IC process with 4.5 kA-per-square cm Josephson junctions and 1.5 micron minimum feature size. The circuit was tested at a derated sample rate of 5 GHz. Measured signal-to-noise dynamic range was 81 dB over a 10 MHz band. Third-order intercept was measured to be +24 dBsat in two-tone test. The measured noise transfer function was in excellent agreement with our linear model. The linear model indicates that with appropriate parameter values, this family of modulators extrapolates to significantly higher performance.

DOI
10.1109/tasc.2009.2018772

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High performance oversampling delta-sigma data converters require high clock rates and accurate feedback of the digital output to the analog regime. Superconductor modulators offer the unique advantages of clock rates in the tens-of-gigahertz, comparator switching energy below attoJoules, and quantum-accurate digital-to-analog feedback. We have designed a two-loop baseband modulator whose noise transfer function was calculated using a simple, linear circuit model. The circuit was fabricated in a commercial superconductor IC process with 4.5 kA-per-square cm Josephson junctions and 1.5 micron minimum feature size. The circuit was tested at a derated sample rate of 5 GHz. Measured signal-to-noise dynamic range was 81 dB over a 10 MHz band. Third-order intercept was measured to be +24 dBsat in two-tone test. The measured noise transfer function was in excellent agreement with our linear model. The linear model indicates that with appropriate parameter values, this family of modulators extrapolates to significantly higher performance.
The sigma-delta architecture is the method of choice for analog-to-digital converters (ADCs) for high dynamic range applications. This architecture uses oversampling and precise feedback to generate a shaped spectral distribution of the quantization noise. Subsequent digital filtering suppresses out-of-band quantization noise, yielding a large signal to in-band noise ratio. A unique advantage of superconducting electronics is the availability of the flux quantum to provide quantum mechanically accurate feedback at GHz rates. Josephson digital technology extends sigma-delta ADCs from MHz sampling rates to GHz sampling rates, from kHz signal bandwidths to MHz signal bandwidths, with comparable or better dynamic range when compared to semiconductor implementations. This paper presents circuits for Josephson sigma-delta ADCs, including single-loop and double-loop modulators operating at sampling rates up to 2 GHz, and circuits for quantized feedback. The first demonstration of double-loop noise shaping is also presented.
Superconducting digital circuits are capable of producing high dynamic range analog-to-digital converters (ADCs). We present sigma-delta architectures using large (>100) oversampling ratios to give signal-to-noise ratios of greater than 100 dB in simulation. Three distinct designs, using two distinct mechanisms for feedback, are presented. All of the designs use only shunted junctions, and are therefore compatible with HTS SNS junctions. Simulations are presented for a modulator which creates feedback pulses by SQUID lobe-crossings, a modulator which uses the transresistance of a SQUID for feedback, and a modulator which uses threshold crossings in both the first and second loops for feedback.
This paper presents a superconducting bandpass /spl Delta//spl Sigma/ modulator for direct analog-to-digital conversion of radio frequency signals in the gigahertz range. The design, based on a 2.23-GHz microstrip resonator and a single flux quantum comparator, exploits several advantages of superconducting electronics: the high quality factor of resonators, the fast switching speed of the Josephson junction, natural quantization of voltage pulses, and high circuit sensitivity. The modulator test chip includes an integrated acquisition memory for capturing output data at sampling rates up to 45 GHz. The small size (256 b) of the acquisition memory limits the frequency resolution of spectra based on standard fast Fourier transforms. Output spectra with enhanced resolution are obtained with a segmented correlation method. At a 42.6-GHz sampling rate, the measured SNR is 49 dB over a 20.8-MHz bandwidth, and a full-scale (FS) input is -17.4 dBm. At a 40.2-GHz sampling rate, the measured in-band noise is -57 dBFS over a 19.6-MHz bandwidth. The modulator test chip contains 4065 Josephson junctions and dissipates 1.9 mW at T=4.2 K.
A wide variety of applications, ranging from radio-frequency (RF) receivers for broadband communications and signal detection, on earth and in space, would benefit from high-performance superconductor analog-to-digital converters (ADCs), based on magnetic flux quantization and fast switching Josephson junctions. Superconductor ADCs are capable of very high sample rates (100 GHz or more), very high linearity, and high sensitivity. Nyquist-rate ADCs use the high sample rate to digitize a wide instantaneous bandwidth (tens of GHz) and are useful for wideband spectrum monitoring as well as high-end scientific instrumentation. Delta and delta-sigma oversampling ADCs use the high linearity to achieve programmable trade-off between dynamic range and instantaneous bandwidth. These lowpass and bandpass ADCs have been used for direct digitization of narrower (tens to hundreds of MHz) RF bands in the 1-20 GHz range for a variety of communications, intelligence, electronic warfare, and radar applications. Another application area of these cryogenic ADCs is for outputs of cryogenic sensor arrays and terahertz mixers. Recent advances in various classes of ADCs for different applications are described.
We designed a superconducting front-end circuit for an analog-to-digital converter and experimentally evaluated its signal-to-noise-ratio (SNR) at a sampling frequency of 10 GHz. The modulator was based on a first-order sigma-delta modulation with an LR integrator. Correct noise shaping was experimentally confirmed, and an SNR of 70.9 dB at a bandwidth of 10 MHz was achieved. In the circuit design, we investigated the effect of leakage in the LR integrator and thermal noise on the SNR by using transfer function analysis and circuit simulations with noise sources. Circuit parameters were designed to keep the discrepancy of the SNR from the ideal value (77.6 dB) within 6 dB. In the experimental evaluation, the modulated data signal from the superconducting chip was accumulated with room-temperature electronics. A fast Fourier transform (FFT) calculation was performed to obtain power spectra and SNRs. The power spectra and SNRs were consistent with the predictions of the transfer function analysis and circuit simulations.
Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. We report recent advances in the low-pass phase-modulation-demodulation (PMD) oversampled analog-to-digital converter (ADC). The oversampled data from the PMD front-end are passed along with sampling clock to an on-chip digital filter. In the past, the maximum frequency of operation of such chips were limited by that of the digital decimation filter (DDF) to about 30 GHz. Recently, we have designed a chip that allows the PMD front-end to be clocked twice as fast as the DDF, resulting in sampling rates of 46.08 GHz and 29.44 GHz for chips with critical current densities of 4.5 and 1 kA/cm2respectively. We have also designed a new PMD front-end, with a quarter-rate quantizer (QRQ) that allows 18-20 dB extension of dynamic range. We are also pursuing a subranging ADC design with two PMD front-ends connected with fluxon amplifier and subtractor circuitry that promises a dynamic range extension by 25-30 dB. We report signal-to-noise ratio and spur-free dynamic range measurement results for various ADC chips, and project performance for future improvements.