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IEEE Transactions on Magnetics

Dynamic threshold characteristics of Josephson switching gates

Michitada Morisue, K. Isaji, M. Kaneko

Published Mar 1, 1985• 1 citation
Publisher

Abstract

This paper describes the dynamic threshold characteristics of Josephson switching gates. When high speed input signals are applied to the Josephson logic gate, the threshold characteristics of the gate are not always in accord with the well-known static threshold curves. This is because the static threshold curves are affected by quantum flux change in Josephson junctions under the high speed operation. The dynamic threshold characteristics of two typical logic gates, one is the CIL gate and the other the interferometer, are described in detail.

DOI
10.1109/tmag.1985.1063868

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This paper describes the dynamic threshold characteristics of Josephson switching gates. When high speed input signals are applied to the Josephson logic gate, the threshold characteristics of the gate are not always in accord with the well-known static threshold curves. This is because the static threshold curves are affected by quantum flux change in Josephson junctions under the high speed operation. The dynamic threshold characteristics of two typical logic gates, one is the CIL gate and the other the interferometer, are described in detail.
Abstract New interferometer direct‐coupled Josephson logic gates are proposed which have good input‐output signal separation and stable, high‐gain, wide‐margin operation. Formulas for evaluating the threshold characteristics and conditions for high gain and high sensitivity are derived. Dynamic properties such as switching times and waveforms are obtained by computer simulation. These gates were tested‐fabricated with a lead alloy whose properties agreed with the results of computer simulation: sensitivity was 2.5 over a bias range of more than 50%. Thus, they can be used as basic logic elements in buffers and OR gates.
This paper proposes a two-junction interferometer called Variable Threshold Logic. It has both magnetically-coupled control-lines and current-injection terminals. The threshold curve of this gate can be shifted by the applied currents. This property enables its use for both OR and AND function with the same structure by only changing the wiring. Operating margins of ±12 % for OR and ± 29 % for AND are obtained with the optimized device parameters. Any logic circuit can be obtained by Josephson master-slice LSI of this gate with a dual-rail logic system.
A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.
The gate delay of a single CIL AND gate is measured with a Josephson sampler. The CIL gate consists of a CIL interferometer preceded by a three-junction SQUID isolation stage. The smallest delay observed was 6 ps. Simulation results and sampling measurements of a gate designed to switch to 3Vgare also reported. Processing variations precluded successful operation of the higher-voltage gate. The simulations suggest that this failure is due to the large difference of the average critical current from the design value. Scaling arguments show that for small-scale circuits high-speed operation with gate delays of a few picoseconds can be achieved with junction dimensions approximately equal to the Josephson penetration depth.
The design and experimental investigation of a simple logic circuit employing Josephson tunnel junctions as the switching elements is described. The design utilized matched transmission lines as signal carriers. The physical layout was simulated on a computer with a model consisting of 3 Josephson gates and 28 transmission line segments. Results of both quasi-static and high speed testing were found to be in essential agreement with theoretical expectations; only dynamic results are presented here in detail. The experimental circuit had gates with 165 ps risetimes, and in the high speed investigation, was operated with bursts of 700 ps risetime pulses tightly spaced so as to simulate a repetition rate of ∼1 GHz.