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Superconductor Science and Technology

Low-jitter on-chip clock for RSFQ circuit applications

Yongming Zhang, Deepnarayan Gupta

Published Nov 1, 1999• 13 citations
Publisher

Abstract

The ultra-narrow linewidth of a long Josephson junction (LJJ) oscillator offers low timing jitter as a clock source. In this paper, we will discuss the improvement of an LJJ clock by using an annular geometry. We demonstrate the integration of an annular LJJ with a clock decimator which consists of a serial chain of toggle-flip-flops (TFFs). Each TFF divides its input frequency by a factor of 2. We have also developed a clock frequency selector. The clock selector circuit can choose either the master clock f m or one of its sub-harmonics ( f m /2 m , m = 1 to n ), based on the select inputs. The generation of a set of clocks will enable us to integrate the on-chip LJJ clock with a flash analogue-to-digital converter.

DOI
10.1088/0953-2048/12/11/323

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An on-chip, low-jitter clock technology is essential for future multi-GHz digital electronics. In this article, we describe an on-chip clock technology for superconducting rapid single flux quantum (RSFQ) circuits built around an unshunted long Josephson junction (LJJ) oscillator that acts as a master clock source. The clock technology also includes clock frequency divider and selector circuits as well as a clock distribution network. These LJJ oscillators, implemented in linear and annular geometries using 3 μm Nb technology, have quality factors of 106. This clock technology potentially has widespread use in 10–100 GHz superconducting digital circuits and systems, including analog-to-digital converters, time-to-digital converters, correlators, and processors for ultrahigh performance computers.

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IEEE Transactions on Applied Superconductivity•Jun 1, 2003•4 citations
The ultra-narrow linewidth of a long Josephson junction (LJJ) oscillator offers low timing jitter as a clock source. In this paper, we will discuss the improvement of an LJJ clock by using an annular geometry. We demonstrate the integration of an annular LJJ with a clock decimator which consists of a serial chain of toggle-flip-flops (TFFs). Each TFF divides its input frequency by a factor of 2. We have also developed a clock frequency selector. The clock selector circuit can choose either the master clock f m or one of its sub-harmonics ( f m /2 m , m = 1 to n ), based on the select inputs. The generation of a set of clocks will enable us to integrate the on-chip LJJ clock with a flash analogue-to-digital converter.
An on-chip, low-jitter clock technology is essential for future multi-GHz digital electronics. In this article, we describe an on-chip clock technology for superconducting rapid single flux quantum (RSFQ) circuits built around an unshunted long Josephson junction (LJJ) oscillator that acts as a master clock source. The clock technology also includes clock frequency divider and selector circuits as well as a clock distribution network. These LJJ oscillators, implemented in linear and annular geometries using 3 μm Nb technology, have quality factors of 106. This clock technology potentially has widespread use in 10–100 GHz superconducting digital circuits and systems, including analog-to-digital converters, time-to-digital converters, correlators, and processors for ultrahigh performance computers.
We have developed clock sources for rapid single flux quantum (RSFQ) digital circuits using high-quality long Josephson junction (LJJ) resonant oscillators of annular geometry. Being a topologically closed system and unperturbed by reflections from boundaries and collisions among the fluxons (flux quanta), the annular LJJ oscillator has demonstrated a high quality factor. The novel design of an annular junction clock that allows easier interface with RSFQ circuitry has been realized. Magnetic fluxons are inserted into an annular LJJ by local injection of current into the control line of the junction. This technique resolves the long-standing problem of achieving superior stability of the fluxon state for application as a clock source. The linewidth of the phase-locked clock source is measured as low as 24 Hz relative to a reference oscillator at 40 GHz. The cycle-to-cycle jitter was measured to be 9 fs at a frequency of 36 GHz, or 0.04% of the clock period which is in good agreement with theoretical estimation.
On-chip, high-frequency clock sources are essential for the future development of superconductor digital circuits and systems. We have developed clock sources for rapid single flux quantum (RSFQ) digital circuits using high-quality long Josephson junction (LJJ) resonant oscillators that offer extremely low jitter. To meet the requirement for time-interleaved clock signals of complementary phase, two-phase 30 and 50 GHz clock sources using LJJ's have been developed with both linear and annular geometry. Unperturbed by reflections from boundaries and collisions among the fluxons (flux quanta), the annular LJJ oscillator has demonstrated superior stability and higher quality factor (>10/sup 6/) than the linear LJJ oscillator. The LJJ oscillator with linear geometry is easier to interface with RSFQ circuitry since it has well-defined boundaries at either end, facilitating a two-phase clock source. On the other hand, multiple clock phases may be derived from an annular LJJ oscillator by connecting interface circuitry at various points around the circular junction, if the interface circuitry does not interfere with the fluxon(s) in the annular junction. Experimental results for two-phase RSFQ clock sources based on linear and annular LJJ oscillators are presented.
One of the crucial factors in achieving high performance of superconducting integrated circuits, such as analog-to-digital converters (ADCs), is sampling using a high-frequency clock source with a low cycle-to-cycle jitter. As the superconductor ADC technology matures toward more complex designs for higher dynamic range performance, the need for synchronous clocking of multiple comparators continues to grow. Since high-frequency external clock sources are expensive and make a significant contribution to the heat load of the system, a high-frequency and low-jitter on-chip clock source using long Josephson junction (LJJ) is considered the preferred long-term solution. Toward that end, we are working on improving an on-chip 110-GHz clock source based on an unshunted LJJ in annular geometry. Minimizing the additional jitter added by each fan-out of the clock signal is the effort's goal. For synchronous clocking of up to three comparators, we compare clock distribution using superconducting passive transmission lines and a new approach using novel active transmission lines. We also introduce a method of synchronizing LJJ clock source with an external stable oscillator by injection locking.
Stability of Josephson junction clock sources can be a limiting factor in the operation of RSFQ digital and mixed signal circuits. We have developed techniques for the characterization of the short-term stability, i.e., the jitter, of Josephson junction clock sources, and in this paper we present measurements of the jitter for a long Josephson junction soliton oscillator clock. The output frequency of the soliton oscillator was prescaled by using a chain of T flip-flops and using a current bias feedback the oscillator was phase locked to a stable room temperature RP source. Phase noise spectra of the clock signal were measured at the successive stages of the T flip-flop chain and interpreted to infer the cycle-to-cycle jitter of the soliton oscillator. The jitter at the output of the soliton oscillator was measured to be 60 fs at a frequency of 26 GHz, or 0.16% of the period of the clock.
This paper discusses the possible modifications of the flux-flow oscillator, which is a part of an integrated receiver, for use as a precise clock oscillator in RSFQ circuits. At the price of losing tunability, the flux-flow oscillator can be used at resonance modes. To get higher clock rates, a parallel array of 20 identical under-damped Josephson junctions connected by superconducting micro-strip lines can also be used with an SIS mixer to form a phase-locked loop. The array shows a sharp resonance at 600 GHz, which can be used to make a precise on-chip clock. The linewidth of the emitted power of 150 kHz was estimated from the step differential resistance (free-run stability of 2.5 /spl middot/ 10/sup -7/). To convert frequency down to the desired level the array was matched to an over-damped pair of junctions, which form a precise frequency divider. The divider almost does not add any time jitter, thus the linewidth of 15 kHz can be achieved at 60 GHz. The clock stability can be improved by using an on-chip phase-locked-loop (PLL). The main part of the PLL is a phase detector, which can be based on an RSFQ Josephson sampler combined with an RSFQ fast counter. The suggested circuit probably could not compete with an SIS mixer, but significantly simplifies the circuit, and enables an on-chip RSFQ PLL closed by RSFQ frequency meter and DAC.