Optically implementable designs of reversible sequential devices

Davar Kheirandish Taleshmekaeil, Majid Haghparast, Midia Reshadi +1 more

Matthew A. Morrison, Nagarajan Ranganathan

Significant debate exists in the literature with regards to the permissibility of feedback in reversible computing nanotechnologies. Feedback allows for reuse of logical subroutines, which is a desired functionality of any computational device. Determining whether loop back is allowed is paramount to assessing the robustness of reversible logic in any quantum design. In this paper, the fundamental discoveries in entropy and quantum mechanics that serve as the foundations for reversible logic are reviewed. The fundamentals for implementation of reversibility in computing are shown. Then, definitions are presented for a sequential reversible logic structure. A sequential reversible logic structure is proven to have an identical number of feedback-dependent inputs and feedback-producing outputs, and new metrics for measuring the probability of each output state are presented. Using these metrics, the reversibility of each clock cycle of such a device is verified. Therefore, we demonstrate that any reversible logic structure with feedback is physically reversible.

Bahram Dehghan, Abdolreza Roozbeh, Jafar Zare

In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.

Anas N. Al‐Rabadi, Lee W. Casperson

Xuemei Qi, Haihong Zhu, Fulong Chen +2 more

Matthew A. Morrison, Matthew Lewandowski, Nagarajan Ranganathan

Programmable reversible logic is gain wide consideration as a logic design style for modern nanotechnology and quantum computing with minimal impact on circuit heat generation in improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Then, a novel 3*3 programmable UPG gate capable of calculating the universal logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, n-bit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fred kin gate is presented and verified. Next, a novel 4*4 reversible programmable RC gate capable of nine unique logical calculations at low cost and delay is presented and verified. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. These designs are compared to previously existing designs, and their advantages in terms of cost and delay are analyzed. Then, the RMUX is used to improve a reversible SRAM cell we previously presented. The memory cell and comparator are implemented in the design of a Min/Max Comparator device.