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IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

A new CRL gate as super class of Fredkin gate to design reversible quantum circuits

Himanshu Thapliyal, Apeksha Bhatt, Nagarajan Ranganathan

Published Aug 1, 2013• 8 citations
Publisher

Abstract

Conservative reversible logic gate is a reversible logic gate that is reversible in nature and also satisfy the property that there are equal number of 1s in the outputs as in the inputs. In this work, we present a new class of n × n (n inputs and n outputs) conservative reversible logic gate named SCRL (Super Conservative Reversible Logic) gate for the design of reversible quantum circuits. The proposed SCRL gate has 1 control input depending on the value of which it can swap any two n - 1 data inputs, hence is superior to the existing Fredkin gate. In reversible circuits, the constant input bits that are used to realize different logic functions are referred to as ancilla inputs, while the outputs that are neither primary inputs nor contribute to any useful computations are referred to as garbage outputs. As Ancilla inputs and garbage outputs are overhead bits in a reversible circuit, they need to be minimized. Barrel shifter forms an integral component of many computing systems. As an example of using the proposed SCRL gate to design efficient reversible quantum circuits, the design of reversible barrel shifter with zero ancilla inputs and zero garbage outputs is illustrated.

DOI
10.1109/mwscas.2013.6674837

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Conservative reversible logic gate is a reversible logic gate that is reversible in nature and also satisfy the property that there are equal number of 1s in the outputs as in the inputs. In this work, we present a new class of n × n (n inputs and n outputs) conservative reversible logic gate named SCRL (Super Conservative Reversible Logic) gate for the design of reversible quantum circuits. The proposed SCRL gate has 1 control input depending on the value of which it can swap any two n - 1 data inputs, hence is superior to the existing Fredkin gate. In reversible circuits, the constant input bits that are used to realize different logic functions are referred to as ancilla inputs, while the outputs that are neither primary inputs nor contribute to any useful computations are referred to as garbage outputs. As Ancilla inputs and garbage outputs are overhead bits in a reversible circuit, they need to be minimized. Barrel shifter forms an integral component of many computing systems. As an example of using the proposed SCRL gate to design efficient reversible quantum circuits, the design of reversible barrel shifter with zero ancilla inputs and zero garbage outputs is illustrated.
Reversible Logic is an emerging technology; it has hellocious applications in various fields.Reversible logic implementation reduces loss of entropy because of bit manipulations.Conservative reversible logic gate obeys reversible logic rules and also satisfies the property that there is equal number of 1s in the outputs as in the inputs.In this work, modified design of SCRL (Super Conservative Reversible Logic) gate for the design of reversible quantum circuit is presented.The proposed SCRL Integrated Qubit gate has 1 control input which swaps n-1 depending on control input.Barrel shifter forms an integral component of many computing systems.As an example of using the proposed SCRL gate to design efficient reversible quantum circuits, the design of reversible barrel shifter with zero ancilla inputs and zero garbage outputs is illustrated. I.
Reversible Logic is an emerging technology; it has hellocious applications in various fields. Reversible logic implementation reduces loss of entropy because of bit manipulations. Conservative reversible logic gate obeys reversible logic rules and also satisfies the property that there is equal number of 1s in the outputs as in the inputs. In this work, modified design of SCRL (Super Conservative Reversible Logic) gate for the design of reversible quantum circuit is presented. The proposed SCRL Integrated Qubit gate has 1 control input which swaps n-1 depending on control input. Barrel shifter forms an integral component of many computing systems. As an example of using the proposed SCRL gate to design efficient reversible quantum circuits, the design of reversible barrel shifter with zero ancilla inputs and zero garbage outputs is illustrated.
Reversible logic has promising applications in the field of quantum computing, optical computing, low power computing, and other emerging computing technologies. A barrel shifter that can shift and rotate multiple bits in a single cycle is an important component of many computing units. This paper presents the reversible design of bidirectional arithmetic and logical barrel shifter. The proposed design consists of the reversible Fredkin and Feynman gates. The Fredkin gate used in the design of reversible bidirectional arithmetic and logical barrel shifter can implement the 2:1 MUX with minimum quantum cost, minimum number of ancilla bits and minimum number of garbage outputs while the Feynman gate is used to avoid the fanout as fanout is not allowed in the reversible logic. The design is evaluated in terms of number of garbage outputs, quantum cost and number of ancilla bits.
Multiple-valued reversible logic is emerging as a promising computing paradigm as it helps in reducing the width of the reversible or quantum circuits. Further, a barrel shifter that can shift and rotate multiple bits in a single cycle forms the essence of many computing systems. In this paper, we propose an efficient architecture and design of a reversible ternary barrel shifter. The ternary barrel shifter is realized using the Modified Fredkin gates (MFG) and the ternary Feynman gates. The design is evaluated in terms of quantum cost, the number of garbage outputs and the number of ancilla bits. To our knowledge, the use of multiple valued reversible logic for the design of a barrel shifter is being attempted for the first time in the literature.
The reversible logic has promising applications in emerging computing paradigms, such as quantum computing, quantum dot cellular automata, optical computing, etc. In reversible logic gates, there is a unique one-to-one mapping between the inputs and outputs. To generate a useful gate function, the reversible gates require some constant ancillary inputs called ancilla inputs. Also to maintain the reversibility of the circuits some additional unused outputs are required that are referred to as the garbage outputs. The number of ancilla inputs, the number of garbage outputs and quantum cost plays an important role in the evaluation of reversible circuits. Thus minimizing these parameters are important for designing an efficient reversible circuit. Reversible circuits are of highest interest in optical computing, quantum dot cellular automata and quantum computing. The quantum gates perform an elementary unitary operation on one, two or more two-state quantum systems called qubits. Any unitary operation is reversible in nature, and hence, quantum networks are also reversible, to conclude the quantum computers must be built from reversible logic components. The main contribution of this dissertation is the design exploration and application of reversible circuits in emerging nanotechnologies. The emerging technologies explored in this work are 1) Optical quantum computing 2) Quantum computing. The first contribution of this dissertation is Mach-Zehnder interferometer based design of all optical reversible binary adder. The all optical reversible adder design is based on two new optical reversible gates referred as optical reversible gate I (ORG-I) and optical reversible gate II (ORG-II) and the existing all optical Feynman gate. The two new reversible gates ORG-I and ORGI-II have been proposed and can implement a reversible adder with a reduced optical cost which is equal to the number of MZI switches required, less propagation delay, and with zero overhead in terms of number of ancilla inputs and the garbage outputs. The proposed all optical reversible adder design based on the ORG-I and ORG-II reversible gates are compared and shown to be better than the other existing designs of reversible adder proposed in the non-optical domain in terms of number of MZI switches, delay, the number of ancilla inputs and the garbage outputs. The proposed all optical reversible adder will be a key component of an all optical reversible arithmetic logical unit (ALU), that is a quite essential component in a wide variety of optical signal processing applications. In the existing literature, the NAND logic based implementation is the only known implementation available for reversible gates and its functions. There is a lack of research in the direction of NOR logic based implementation of reversible gates and functions. The second contribution of this dissertation is the design of NOR logic based n-input and n-output reversible gates, one of which can be efficiently mapped into optical computing using the Mach-Zehnder interferometer (MZI), while the other can be mapped efficiently in optical computing using the linear optical quantum gates. The proposed reversible NOR gates work as a corresponding NOR counterpart of NAND logic based Toffoli gates. The proposed optical reversible NOR logic gates can implement the reversible boolean logic functions with less number of linear optical quantum logic gates with reduced optical cost and propagation delay compared to the implementation using existing optical reversible NAND gates. It is illustrated that an optical reversible gate library having both optical Toffoli gate and the proposed optical reversible NOR gate is superior compared to the library containing only the optical Toffoli gate: (i) in terms of number of linear optical quantum gates when implemented using linear optical quantum computing (LOQC), (ii) in terms of optical cost and delay when implemented using the Mach-Zehnder interferometer. The third contribution of this dissertation is a binary tree-based design methodology for a NxN reversible multiplier. The proposed binary tree-based design methodology for a NxN reversible multiplier performs the addition of partial products in parallel using the reversible ripple adders with zero ancilla bit and zero garbage bit; thereby, minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows improvements in terms of number of ancilla inputs and garbage outputs compared to all the existing reversible multiplier designs. The methodology is also extended to the design of NxN reversible signed multiplier based on modified Baugh-Wooley multiplication methodology.
Reversible computing is an emerging field of research and has made remarkable progress. Owing to the reduced energy dissipation in reversible circuits, a lot of research has been done on the design of reversible circuits. In reversible logic circuit designs, along with primary inputs, few constant inputs (Ancilla Inputs) are used to realize required reversible functions. In addition to this, few unused or extra output bits are generated; these bits are named as Garbage Output bits. A challenge in the reversible computation is to use minimum Ancilla Inputs and generate zero Garbage Outputs. In this work, we present designs for addition, subtraction, and addition or subtraction operations. The designs are primarily optimized to achieve zero Garbage Outputs and minimum Ancilla Inputs. In addition, these proposed arithmetic circuits are designed for best Gate Count and Quantum Cost values compared to the existing counterparts.