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International Journal of Smart Sensor and Adhoc Network

DESIGN METHODOLOGY OF BIDIRECTIONAL BARREL SHIFTER BASED ON REVERSIBLE LOGIC

Vahini N Srujana, Gara Uday Bhaskar Babu

Published Jul 1, 2013• 1 citation
Publisher

Abstract

Data shifting is required in many key computer operations from address decoding to computer arithmetic. Full barrel shifters are often on the critical path, which has led most research to be directed toward speed optimizations. With the advent of quantum computer and reversible logic, design and implementation of all devices in this logic has received more attention. Rotating and data shifting are required in many operations such as logical and arithmetic operations, indexing and address decoding etc. Hence barrel shifters which can shift and rotate multiple bits in a single cycle have become a common choice of design for high speed applications. The design has been done using reversible fredkin and feynman gates. In the design the 2:1 mux can be implemented by fredkin gate which reduce quantum cost, number of ancilla bits and number of garbage outputs. The feynman gate will remove the fanout. By comparing the quantum cost, number of ancilla bits and number of garbage outputs the design is evaluated.

DOI
10.47893/ijssan.2013.1195

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Data shifting is required in many key computer operations from address decoding to computer arithmetic. Full barrel shifters are often on the critical path, which has led most research to be directed toward speed optimizations. With the advent of quantum computer and reversible logic, design and implementation of all devices in this logic has received more attention. Rotating and data shifting are required in many operations such as logical and arithmetic operations, indexing and address decoding etc. Hence barrel shifters which can shift and rotate multiple bits in a single cycle have become a common choice of design for high speed applications. The design has been done using reversible fredkin and feynman gates. In the design the 2:1 mux can be implemented by fredkin gate which reduce quantum cost, number of ancilla bits and number of garbage outputs. The feynman gate will remove the fanout. By comparing the quantum cost, number of ancilla bits and number of garbage outputs the design is evaluated.
Reversible logic has promising applications in the field of quantum computing, optical computing, low power computing, and other emerging computing technologies. A barrel shifter that can shift and rotate multiple bits in a single cycle is an important component of many computing units. This paper presents the reversible design of bidirectional arithmetic and logical barrel shifter. The proposed design consists of the reversible Fredkin and Feynman gates. The Fredkin gate used in the design of reversible bidirectional arithmetic and logical barrel shifter can implement the 2:1 MUX with minimum quantum cost, minimum number of ancilla bits and minimum number of garbage outputs while the Feynman gate is used to avoid the fanout as fanout is not allowed in the reversible logic. The design is evaluated in terms of number of garbage outputs, quantum cost and number of ancilla bits.
Multiple-valued reversible logic is emerging as a promising computing paradigm as it helps in reducing the width of the reversible or quantum circuits. Further, a barrel shifter that can shift and rotate multiple bits in a single cycle forms the essence of many computing systems. In this paper, we propose an efficient architecture and design of a reversible ternary barrel shifter. The ternary barrel shifter is realized using the Modified Fredkin gates (MFG) and the ternary Feynman gates. The design is evaluated in terms of quantum cost, the number of garbage outputs and the number of ancilla bits. To our knowledge, the use of multiple valued reversible logic for the design of a barrel shifter is being attempted for the first time in the literature.
Reversible logic attains the dominance in the realm of overwhelming research in logic synthesis and also has the significance in the context of quantum computing because of loss-less information processing. Due to low power dissipation, researchers are first designing smaller components with reversible gates, that eventually lead to design reversible computer. In this paper, we propose a robust architecture of logarithmic barrel shifter that performs bidirectional arithmetic and logical shifting, including rotate operation. Incorporating fault tolerance capability, the circuit is designed very efficiently that exhibits superior performance over state-of-the-art design methods in terms of minimum number of gates, garbage outputs, ancilla inputs, quantum cost, delay and others cost factors.
A barrel shifter is a common component in the high-speed processor.It can shift a data word by specified number of bits in one clock cycle.Based on the quantum reversible logic circuit,the shifter with n inputs and m control bits named as a(n,m) shifter.For synthesizing the reversible shifter,the novel method based on the decomposition of the permutation group,it only use(3,1) shifters and controlled swap gates to quickly synthesize any controlled shifter with small quantum cost,and any(n,k) barrel shifter can be obtained by cascading minimal k corresponding(n,1) shifters.
Reversible Logic is an emerging technology; it has hellocious applications in various fields.Reversible logic implementation reduces loss of entropy because of bit manipulations.Conservative reversible logic gate obeys reversible logic rules and also satisfies the property that there is equal number of 1s in the outputs as in the inputs.In this work, modified design of SCRL (Super Conservative Reversible Logic) gate for the design of reversible quantum circuit is presented.The proposed SCRL Integrated Qubit gate has 1 control input which swaps n-1 depending on control input.Barrel shifter forms an integral component of many computing systems.As an example of using the proposed SCRL gate to design efficient reversible quantum circuits, the design of reversible barrel shifter with zero ancilla inputs and zero garbage outputs is illustrated. I.