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Journal of Applied Physics

Minimization of thermal jitter in a balanced comparator single flux quantum cell

Anna V. Gordeeva, A. L. Pankratov

Published May 15, 2008• 10 citations
Publisher

Abstract

The process of reproduction of single flux quantum pulses in a Josephson junction chain composed of a pulse generator, a balanced comparator, and a single Josephson junction is investigated. It is shown that the reproduction of single flux quantum pulses in such a chain is more stable and the mean and the standard deviation of switching time are minimal for the McCumber-Stewart parameter value from 0.5 to 1 and for a normalized clock generator current around 1.5. The influence of input and output inductances on the characteristics of a balanced comparator is investigated. The recommended value of the output inductance leading to smooth pulses and relatively small jitter is around unity.

DOI
10.1063/1.2931007

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Investigations of Josephson junction parameters for Rapid Single

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Abstract\nThis diploma work is about Rapid Single Flux Quantum (RSFQ) circuits. This\nsupercoducting digital circuitry has the most promising properties in terms of speed and\npower consumption. The active elements of the RSFQ circuits are Josephson junctions (JJ).\nFor their fabrication low temperature superconducting niobium films are used. Today the\ndesign and fabrication of RSFQ circuits are done in a standardized way with well-defined\ndesign rules. Nevertheless, to design complicated circuits with more than several hundred\njunctions a lot of practical problems must be solved.\nDifferent aspects of the RSFQ circuits design process were investigated in this work.\nIn the theoretical part we propose a new, more realistic model of the Josephson junction for\nphysical simulation (which is necessarily used for design of every RSFQ gate) in order to\nimprove its quality and precision. The new model for the JJ includes additional inductances,\nwhich must reflect a specific environment of the junction layout. The influence of parameter\ndeviations was investigated in the simulation. As sources of the deviation we chose the\nspread of c (the Stewart-McCumber parameter) and that of the inductances. Then the\noperational margins of the basic elements of the RSFQ logic SR flip-flop were determined\nand compared with the prediction of the previously used model. To prove the results of\nsimulations we designed a test structure of the SR flip-flop, with c=1 and c=2 for the wellestablished\nHYPRES technology (USA).\nAnother part of the work is practical measurements. A test chip, containing chains of 100\nJosephson junctions was designed and measured in order to estimate the spread of critical\ncurrents in real technology.

•Jan 1, 2003•0 citations
The process of reproduction of single flux quantum pulses in a Josephson junction chain composed of a pulse generator, a balanced comparator, and a single Josephson junction is investigated. It is shown that the reproduction of single flux quantum pulses in such a chain is more stable and the mean and the standard deviation of switching time are minimal for the McCumber-Stewart parameter value from 0.5 to 1 and for a normalized clock generator current around 1.5. The influence of input and output inductances on the characteristics of a balanced comparator is investigated. The recommended value of the output inductance leading to smooth pulses and relatively small jitter is around unity.
We consider the time characteristics of a balanced comparator formed by two Josephson junctions connected in series. Such a decision-making junction pair is an essential component of all RSFQ cells. The analysis is performed within the framework of a simple time-dependent oscillator model. Turn-on delay and uncertainty (jitter) of comparator switching times are analysed taking into account the influence of thermal fluctuations and the finite time duration of clock pulse. Restrictions on speed performance of RSFQ cells caused by both times are considered. Some practical recommendations on the clock frequency increase are also discussed.
We evaluated timing jitter based on a time-to-digital converter (TDC) having sub-pico seconds time resolution. The measured jitter at liquid helium temperature was 65 fs for an optimally damped simple junction composing a conventional Josephson transmission line fabricated with the NEC standard process. The temperature dependence and shunt resistance dependence of jitter indicate that the jitter originates from thermal noise generated at the shunt resistor of the junction. We also found that the timing jitter of a balanced comparator is much larger than that of a JTL. The jitter of a balanced comparator is independent of temperature. This means that the jitter of a balanced comparator does not arise from thermal noise.
The balanced comparator, a pair of Josephson junctions, is a key building block and decision-making element for the Rapid Single Flux Quantum (RSFQ) logic cells. The properties of the balanced comparator (BC) define the maximum clock frequency and bit error rate (BER) of RSFQ cells and circuits. Comparators are well characterized by two parameters, the gray zone (GZ) and the gray zone threshold (GZT). Both parameters depend on the dynamic properties of a pair of junctions forming the BC and its surrounding circuitry. In addition, the gray zone depends on the thermal noise in Josephson junctions. The GZ and GZT parameters can be easily measured for various balanced comparators and be used for model-to-hardware correlations. This makes the balanced comparator a unique circuit to validate and calibrate any Josephson simulator by comparing measured and simulated characteristics, including both dynamic and noise properties. In this paper we used a set of balanced comparators designed for the SFQ5ee fabrication process at MIT Lincoln Laboratory to validate and calibrate the Synopsys PrimeSim HSPICE simulator. We were able to match experimental and simulated results and reproduce in simulations the main features observed experimentally and predicted theoretically. A list of recommended design variations to validate a Josephson simulator is provided.
Abstract\nThis diploma work is about Rapid Single Flux Quantum (RSFQ) circuits. This\nsupercoducting digital circuitry has the most promising properties in terms of speed and\npower consumption. The active elements of the RSFQ circuits are Josephson junctions (JJ).\nFor their fabrication low temperature superconducting niobium films are used. Today the\ndesign and fabrication of RSFQ circuits are done in a standardized way with well-defined\ndesign rules. Nevertheless, to design complicated circuits with more than several hundred\njunctions a lot of practical problems must be solved.\nDifferent aspects of the RSFQ circuits design process were investigated in this work.\nIn the theoretical part we propose a new, more realistic model of the Josephson junction for\nphysical simulation (which is necessarily used for design of every RSFQ gate) in order to\nimprove its quality and precision. The new model for the JJ includes additional inductances,\nwhich must reflect a specific environment of the junction layout. The influence of parameter\ndeviations was investigated in the simulation. As sources of the deviation we chose the\nspread of c (the Stewart-McCumber parameter) and that of the inductances. Then the\noperational margins of the basic elements of the RSFQ logic SR flip-flop were determined\nand compared with the prediction of the previously used model. To prove the results of\nsimulations we designed a test structure of the SR flip-flop, with c=1 and c=2 for the wellestablished\nHYPRES technology (USA).\nAnother part of the work is practical measurements. A test chip, containing chains of 100\nJosephson junctions was designed and measured in order to estimate the spread of critical\ncurrents in real technology.