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Superconductor Science and Technology

Time characteristics of a Josephson-balanced comparator

Timur V. Filippov, M Znosko

Published Nov 1, 1999• 12 citations
Publisher

Abstract

We consider the time characteristics of a balanced comparator formed by two Josephson junctions connected in series. Such a decision-making junction pair is an essential component of all RSFQ cells. The analysis is performed within the framework of a simple time-dependent oscillator model. Turn-on delay and uncertainty (jitter) of comparator switching times are analysed taking into account the influence of thermal fluctuations and the finite time duration of clock pulse. Restrictions on speed performance of RSFQ cells caused by both times are considered. Some practical recommendations on the clock frequency increase are also discussed.

DOI
10.1088/0953-2048/12/11/325

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We consider the time characteristics of a balanced comparator formed by two Josephson junctions connected in series. Such a decision-making junction pair is an essential component of all RSFQ cells. The analysis is performed within the framework of a simple time-dependent oscillator model. Turn-on delay and uncertainty (jitter) of comparator switching times are analysed taking into account the influence of thermal fluctuations and the finite time duration of clock pulse. Restrictions on speed performance of RSFQ cells caused by both times are considered. Some practical recommendations on the clock frequency increase are also discussed.
The use of high-T/sub c/ Josephson junctions for digital applications requires a careful study of the influence of thermal noise on circuit performance. We investigated a balanced current comparator, which contains a basic component of all RSFQ circuits: two overdamped Josephson junctions connected in series. The dependence of the dc-voltage across the Josephson junctions on signal current was measured to determine the threshold uncertainty of switching of the comparator. The experimental data obtained at different sampling pulse frequencies, in a temperature range from 10 to 50 K, were compared with a theoretical model, taking into account the influence of thermal noise as well as of sampling pulse frequency.
The process of reproduction of single flux quantum pulses in a Josephson junction chain composed of a pulse generator, a balanced comparator, and a single Josephson junction is investigated. It is shown that the reproduction of single flux quantum pulses in such a chain is more stable and the mean and the standard deviation of switching time are minimal for the McCumber-Stewart parameter value from 0.5 to 1 and for a normalized clock generator current around 1.5. The influence of input and output inductances on the characteristics of a balanced comparator is investigated. The recommended value of the output inductance leading to smooth pulses and relatively small jitter is around unity.
The balanced comparator, a pair of Josephson junctions, is a key building block and decision-making element for the Rapid Single Flux Quantum (RSFQ) logic cells. The properties of the balanced comparator (BC) define the maximum clock frequency and bit error rate (BER) of RSFQ cells and circuits. Comparators are well characterized by two parameters, the gray zone (GZ) and the gray zone threshold (GZT). Both parameters depend on the dynamic properties of a pair of junctions forming the BC and its surrounding circuitry. In addition, the gray zone depends on the thermal noise in Josephson junctions. The GZ and GZT parameters can be easily measured for various balanced comparators and be used for model-to-hardware correlations. This makes the balanced comparator a unique circuit to validate and calibrate any Josephson simulator by comparing measured and simulated characteristics, including both dynamic and noise properties. In this paper we used a set of balanced comparators designed for the SFQ5ee fabrication process at MIT Lincoln Laboratory to validate and calibrate the Synopsys PrimeSim HSPICE simulator. We were able to match experimental and simulated results and reproduce in simulations the main features observed experimentally and predicted theoretically. A list of recommended design variations to validate a Josephson simulator is provided.
The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured. Its noise properties are crucial for the performance of logic devices. The balanced comparator can also be used to monitor the fab process and design implementation as an indicator of excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure the comparator gray zone at different fabrication process nodes at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies. An analog testbed was used to perform high-frequency characterization. Experimental results for different current densities, sheet resistances, damping and clock frequencies are presented.
The Josephson comparator is one of the fundamental building blocks of rapid single flux quantum (RSFQ) electronics. Within this circuit family it is the exclusive device which provides logical data processing. The Josephson comparator is also the basic decision element for very fast analog-to-digital converters and sampler circuits for low input power and high-bandwidth signals based on the RSFQ technique. The performance of those devices is fundamentally determined by the characteristics of the Josephson comparator. In this study the gray zone dependency on the clock frequency of a Josephson comparator is investigated by simulations concerning the influence of thermal noise. This investigation is performed for a series of operating points defined by the bias current and different noise levels defined by the operating temperature. In contrast to former investigations, we analyzed the comparator embedded in a realistic environment for output data processing. We identified a characteristic clock frequency f c for a comparator topology designed for a 1 kA cm − 2 niobium fabrication technology. The gray zone of 8 µA remains constant for clock frequencies below f c = 15 GHz and starts to increase for larger frequencies. We also found out that this characteristic frequency is independent of the intensity of thermal noise and therefore independent of temperature.
The sensitivity of a balanced comparator composed of two overdamped Josephson junctions fed by single flux pulses is calculated, taking into account both thermal and quantum fluctuations. The results of the analysis are compared with those of recent experiments. Ultimate resolution of the balanced comparator with feasible junction parameters is estimated to be as high as approximately 50 pA/Hz/sup 1/2/ at 4 K and approximately 10 pA/Hz/sup 1/2/ at T to 0 K. Performance limits of the device are compared with those of its single-junction counterpart.