Applied Physics Letters

A superconducting sampler for Josephson logic circuits

C.A. Hamilton, Frances L. Lloyd, Rick Peterson, J. R. Andrews

Published Nov 1, 1979• 45 citations

Abstract

A method is described for automating a technique which is used to sample transition duration (rise time) in superconducting logic circuits. The method is based on measuring the time at which a biased Josephson junction switches under the influence of an applied signal. The system transition duration is limited primarily by time jitter which is estimated to be 7 ps. Transition durations of as little as 9 ps have been observed.

DOI: 10.1063/1.91266

Related papers

Picosecond Josephson samplers: Modeling and measurements

Logan A. Howe, Bart J. Van Zeghbroeck, David I. Olaya +4 more

Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler that balances the highest sampler bandwidth (shortest 10%-90% rise time) with minimal sampled waveform distortion. We explore the impacts on the performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations, we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time [or full width at half maximum (FWHM)] as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results, we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and an impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique, the system is fully digital and automated, and the operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10%-90% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear system analysis of sampled waveforms indicates a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this-as high as 600 GHz.

Review of Scientific InstrumentsJun 1, 20250 citations

Picosecond Josephson Samplers: Modeling and Measurements

Logan A. Howe, Bart van Zeghbroeck, David I. Olaya +4 more

Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler which balances the highest sampler bandwidth (shortest 10\%--90\% rise time) with minimal sampled waveform distortion. We explore the impacts on performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time (or FWHM) as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique the system is fully-digital and automated and operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10\%--90\% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear systems analysis of sampled waveforms indicate a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this -- as high as 600 GHz.

arXiv:2503.20022Mar 25, 20250 citations

A Josephson ultrahigh-resolution sampling system

David B. Tuckerman

An ultrahigh-resolution Josephson-technology sampling system has been designed and tested. A complex test signal containing a 10-ps rise time was measured and agreed very well with the signal expected from simulations. The intrinsic rise time (step response) of the sampling system is believed to be about 6 ps. External analog circuitry was used to automate the system.

Applied Physics LettersJun 15, 198057 citations

Technology Related Timing Jitter in Superconducting Electronics

Thomas Ortlepp, Friedrich Uhlmann

Digital superconducting systems based on Josephson junctions make generally use of the synchronous timing strategy. Today, one of its most promising applications is the high speed and high dynamic range signal sensing. A digital signal acquisition system should have a high resolution as well as a short sampling interval with a well known and constant time period. Short term clock fluctuations (clock jitter) induced by thermal noise can significantly disturb the system operation due to hazards of timing constraint violations. This uncertainty in the time period is currently a strong limitation for further improvements of fast signal sensing systems based on superconductive electronics. Recently, several theoretical and experimental studies describe the timing jitter in simple circuits, like Josephson transmission lines. In the presented work, we analyse different fabrication technologies for rapid single flux quantum (RSFQ) electronics and predict their timing jitter by the numerical solution of stochastic differential equations. We obtained a very good agreement between our simulation data and recent experimental results.

IEEE Transactions on Applied SuperconductivityJun 1, 200725 citations

Electronically adjustable delay for Josephson technology

R. Harris, P. Wolf, David F. Moore

An electronically adjustable time delay circuit for superconducting technology is reported. In conjunction with a superconducting sampler on the same chip, the delay circuit has allowed measurement of waveforms with an apparent resolution of 8.5 ps. The delay circuit permits flicker-free oscilloscope displays of fast waveforms, and provides the circuitry needed for further speed advances in superconducting sampling and other ultra-fast measurement techniques.

IEEE Electron Device LettersSep 1, 198227 citations

An elementary logic circuit employing superconducting Josephson tunneling gates

W.H. Henkels

The design and experimental investigation of a simple logic circuit employing Josephson tunnel junctions as the switching elements is described. The design utilized matched transmission lines as signal carriers. The physical layout was simulated on a computer with a model consisting of 3 Josephson gates and 28 transmission line segments. Results of both quasi-static and high speed testing were found to be in essential agreement with theoretical expectations; only dynamic results are presented here in detail. The experimental circuit had gates with 165 ps risetimes, and in the high speed investigation, was operated with bursts of 700 ps risetime pulses tightly spaced so as to simulate a repetition rate of ∼1 GHz.

IEEE Transactions on MagneticsSep 1, 197429 citations