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Superconductor Science and Technology

An improved technique for the design of Josephson transmission lines

Boyko Dimov, Valery Todorov, Valeri Mladenov, M. Khabipov, D Balashov, Daniel Hagedorn, F-Im Buchholz, J. Niemeyer, Friedrich Uhlmann

Published Feb 27, 2006• 2 citations
Publisher

Abstract

Recently, we have proposed a novel technique for the design of Josephson transmission lines (JTLs). According to our theoretical estimations, this technique is able to increase the propagation speed of the JTLs and to reduce drastically their dc bias consumption. Here, a successful experimental verification of these estimations is presented.

DOI
10.1088/0953-2048/19/5/s10

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Recently, we have proposed a novel technique for the design of Josephson transmission lines (JTLs). According to our theoretical estimations, this technique is able to increase the propagation speed of the JTLs and to reduce drastically their dc bias consumption. Here, a successful experimental verification of these estimations is presented.
An important precondition for the successful realization of any high-speed complex electronic device are the efficient (in terms of speed and signal degradation) long-distance interconnects. The two techniques for long-distance on-chip signal propagation, used by the modern rapid single flux quantum (RSFQ) designers - via Josephson transmission lines (JTLs) and via passive transmission lines (PTLs) - are investigated here. Novel design techniques are presented, which significantly improve the JTLs and PTLs performance as long-distance SFQ pulse transmitters within the digital RSFQ circuits.
Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, a novel design method that enables a wide operating margin at a high operating frequency has been investigated. The proposed circuits incorporate an additional bias feeding line in addition to the conventional bias feeding lines of the conventional Josephson transmission lines (JTLs) and can control the dependence of signal propagation time on the bias voltage. We have shown experimentally that in our proposed JTLs, the signal propagation time becomes more sensitive to the bias voltage. Timing errors can be avoided by inserting proposed JTL cells in the critical data path of the SFQ digital circuits. Circuit simulation results indicate that the operating margin of a bit-serial SFQ full adder, designed assuming the 2.5 kA/cm2Nb process, can be improved by 15% compared with the conventional design at a frequency of 20 GHz by employing our novel design method.
Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeoff between circuit activity, energy efficiency, and bias margins for zero static power dissipation ERSFQ circuits. For ERSFQ, dc power is provided by a Josephson transmission line (JTL) called a “feeding” JTL (FJTL), which acts as a voltage source. As a test case, shift registers and multiplexers were laid out and fabricated in both HYPRES's and MIT-LL's 10-kA/cm2fabrication processes and tested at low (~kHz) and high (~GHz) clock frequencies. The functional bias margins for these circuits increase significantly from +/-4% to over +/-19% when the Josephson junction count in the FJTL was increased to ~30% of total dc bias current of the circuit. Based on our findings, we discuss how to optimize ERSFQ circuits for both energy efficiency and dc bias margins.