An important precondition for the successful realization of any high-speed complex electronic device are the efficient (in terms of speed and signal degradation) long-distance interconnects. The two techniques for long-distance on-chip signal propagation, used by the modern rapid single flux quantum (RSFQ) designers - via Josephson transmission lines (JTLs) and via passive transmission lines (PTLs) - are investigated here. Novel design techniques are presented, which significantly improve the JTLs and PTLs performance as long-distance SFQ pulse transmitters within the digital RSFQ circuits.
An important precondition for the successful realization of any high-speed complex electronic device are the efficient (in terms of speed and signal degradation) long-distance interconnects. The two techniques for long-distance on-chip signal propagation, used by the modern rapid single flux quantum (RSFQ) designers - via Josephson transmission lines (JTLs) and via passive transmission lines (PTLs) - are investigated here. Novel design techniques are presented, which significantly improve the JTLs and PTLs performance as long-distance SFQ pulse transmitters within the digital RSFQ circuits.
The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of ±29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm2technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.
We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.
To enable the use of passive transmission lines (PTLs) for the interconnection of single-flux-quantum (SFQ) circuits, we have implemented a driver and a receiver and have developed a method for designing SFQ circuits with passive interconnections. Basic components and properties of passive interconnections, such as the frequency characteristics of the driver and receiver, the PTL delay, and the crosstalk between PTLs, have been experimentally verified. Our developed components and design method have been applied to actual SFQ circuits, such as a 4 x 4 switch having block-to-block passive interconnections and a 2 x 2 switch having gate-to-gate passive interconnections. We have also shown the advantages of PTLs over Josephson transmission lines (JTLs). We also discuss the prospects of SFO circuits having passive interconnections.
We have developed a method of designing single-flux-quantum (SFQ) logic circuits with passive gate-to-gate interconnections. Based on our method, we designed a 2/spl times/2 switch in which all the interconnections are implemented with passive transmission lines (PTLs) while short Josephson transmission line (JTL) segments are used only to adjust the signal timings. Compared with an identical switch using JTL interconnections, the switch using PTL interconnections has 45% fewer wiring junctions and requires 48% less wiring power current. The switch operated at 40 GHz with a bias margin of /spl plusmn/9.5%.
The introduction of passive-transmission-line (PTL) wiring to large-scale SFQ logic circuits offers several advantages over traditional Josephson-transmission-line (JTL) wiring, such as smaller wiring area, less delay, lower power consumption, and more freedom in routing. PTL wiring can drastically change the style of designing SFQ logic circuits. We propose a new methodology for designing large-scale SFQ circuits using PTL wiring. Aiming at generalizing SFQ circuit design, we chose synchronous clocking. We developed a placer that was suitable for SFQ circuit design to assist us with the new design methodology. The placer first synthesizes an H-tree clock distribution network, placing SFQ pulse splitter cells at each branch. It then places logic cells to minimize the maximum length of data PTL wires, aiming at higher operating speeds. Finally, a router completes the PTL wiring. To evaluate the design methodology we designed an 8-bit general purpose RISC processor. Within twelve hours, we obtained a 15-mm-square SFQ circuit that could operate up to 27.6 GHz. We adopted an advanced Nb process, which was characterized by a critical current density of 10 kA/cm2, two 5-mum-wide PTL wiring layers, and a minimum cell size of 30 mum times 30 mum. The circuit consisted of about 20,000 logic cells, which approximated more than 400,000 Josephson junctions including splitters to distribute the clock signal.
Passive transmission lines (PTLs) provide an energy-efficient means of transporting pulsed single flux quantum (SFQ) signals between logic gates and blocks on a chip, or even between chips through a multi-chip module carrier. Although functional up to 70 GHz, our previous designs manifested sharp, length-dependent resonances resulting in diminished operating margins. These are particularly inconvenient since the resonant length is about 1 mm at 40–50 GHz, where most SFQ circuits currently function. To avoid the need to keep the PTLs < 1 mm in length, we have optimized the PTL driver-receiver pairs to sufficiently suppress these resonances; this helps facilitate the use of automated routing tools. We present experimental results, in the 10-70 GHz frequency range, for different driver-receiver pairs designed for PTLs in our dual RSFQ-ERSFQ cell library. This cell library, targeting MIT Lincoln Laboratory's SFQ5ee fabrication process, uses PTLs with two types of ground plane configuration. The first variant has signal in M1 and/or M3 with symmetrical ground planes in M0, M2 and/or M2, M4 respectively. The second variant has signal in M2 and/or M3 with asymmetrical ground planes in M1 and M4. We also present a comparison with wider, 4 Ω, PTLs that are more suitable for transport between distant logic blocks. Next, we present experimental results of PTL lengths ranging from 1.2-12 mm over the same 10-70 GHz frequency range. Finally, we report on the design of circuits for investigating crosstalk between two PTLs and their measurement results.