Parallel Processing Letters

PARALLELIZATION OF REVERSIBLE RIPPLE-CARRY ADDERS

Michael Kirkedal Thomsen, Holger Bock Axelsen

Published Jun 1, 2009• 20 citations

Abstract

The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage. Here, we present a novel parallelization scheme wherein m parallel k-bit reversible ripple-carry adders are combined to form a reversible mk-bit ripple-block carry adder with logic depth [Formula: see text] for a minimal logic depth [Formula: see text], thus improving on the mk-bit ripple-carry adder logic depth [Formula: see text]. The underlying mechanisms of the parallelization scheme are formally proven correct. We also show designs for garbage-less reversible comparison circuits. We compare the circuit costs of the resulting ripple-block carry adder with known optimized reversible ripple-carry adders in measures of circuit delay, width, gate, transistor count, and relative power efficiency, and find that the parallelized adder offers significant speedups at realistic word sizes with modest parallelization overhead.

DOI: 10.1142/s0129626409000171

Related papers

Optimization of Ripple Carry Adder using Quantum Computing

N.Parvatham, Rithiga R, Ruzmina M +1 more

This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.

International Conference on Ubiquitous Computing and Intelligent Information Systems (ICUIS)Nov 26, 20250 citations

Reversible adder design for ripple carry and carry look ahead (4, 8, 16, 32-bit)

Somani Neelam, Chaudhary Chitrita, S. Ramani Yadav

Reversible logic has represented itself as a prominent technology which plays an important role in Quantum Computing. Theoretically Quantum Computers operates at high speed and consumes less power. Furthermore, Reversible logic can break the conventional speed of power trade-off. To prove this we are implementing Ripple Carry Adder and Carry Look Ahead Adder using reversible logic gates. The paper presents efficient adder circuits using Peres gate, New fault Tolerant gate and Double Feyman gate. The complexity, simulated outputs and the speed parameters for the adder circuit have been indicated using the Quartus II 9.1 edition and Modelsim tool. Moreover, the quantum algorithms can potentially solve NP-complete problems. Furthermore, doing high performance functions beyond the limit of deterministic computer systems is possible by only reversible logic. Quantum operations are unitary in nature which is reversible and hence the arithmetic operations like adders can be implemented using the reversible logic. Likewise, optimized block size, minimum ancillary bits, and one to one mappings of inputs and outputs are obtained in the reversible adder circuit, giving fan out as 1. Hence, the Ripple Carry Adder and Carry look Ahead Adder is providing complexity reduction and high speed, proving to be an efficient and important part in the development of arithmetic blocks of Quantum Computers.

International Conference on Computing, Communication and AutomationApr 1, 201612 citations

Design of efficient reversible logic-based binary and BCD adder circuits

Himanshu Thapliyal, Nagarajan Ranganathan

Reversible logic is gaining significance in the context of emerging technologies such as quantum computing since reversible circuits do not lose information during computation and there is one-to-one mapping between the inputs and outputs. In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best values for the quantum cost and delay. In reversible circuits, in addition to the primary inputs, some constant input bits are used to realize different logic functions which are referred to as ancilla inputs and are overheads that need to be reduced. Further, the garbage outputs which do not contribute to any useful computations but are needed to maintain reversibility are also overheads that need to be reduced in reversible designs. First, we propose two new designs for the reversible ripple carry adder: (i) one with no input carry c 0 and no ancilla input bits, and (ii) one with input carry c 0 and no ancilla input bits. The proposed reversible ripple carry adder designs with no ancilla input bits have less quantum cost and logic depth (delay) compared to their existing counterparts in the literature. In these designs, the quantum cost and delay are reduced by deriving designs based on the reversible Peres gate and the TR gate. Next, four new designs for the reversible BCD adder are presented based on the following two approaches: (i) the addition is performed in binary mode and correction is applied to convert to BCD when required through detection and correction, and (ii) the addition is performed in binary mode and the result is always converted using a binary to BCD converter. The proposed reversible binary and BCD adders can be applied in a wide variety of digital signal processing applications and constitute important design components of reversible computing.

arXiv:1712.02630ACM Journal on Emerging Technologies in Computing SystemsSep 1, 2013106 citations

A new reversible design of BCD adder

Himanshu Thapliyal, Nagarajan Ranganathan

Reversible logic is one of the emerging technologies having promising applications in quantum computing. In this work, we present new design of the reversible BCD adder that has been primarily optimized for the number of ancilla input bits and the number of garbage outputs. The number of ancilla input bits and the garbage outputs is primarily considered as an optimization criteria as it is extremely difficult to realize a quantum computer with many qubits. As the optimization of ancilla input bits and the garbage outputs may degrade the design in terms of the quantum cost and the delay, thus the quantum cost and the delay parameters are also considered for optimization with primary focus towards the optimization of the number of ancilla input bits and the garbage outputs. Firstly, we propose a new design of the reversible ripple carry adder having the input carry Co and is designed with no ancilla input bits. The proposed reversible ripple carry adder design with no ancilla input bits has less quantum cost and the logic depth (delay) compared to its existing counterparts. The existing reversible Peres gate and a new reversible gate called the TR gate is efficiently utilized to improve the quantum cost and the delay of the reversible ripple carry adder. The improved quantum design of the TR gate is also illustrated. Finally, the reversible design of the BCD adder is presented which is based on a 4 bit reversible binary adder to add the BCD number, and finally the conversion of the binary result to the BCD format using a reversible binary to BCD converter.

Design, Automation, and Test in EuropeMar 1, 201166 citations

Quantum Efficient Reconfigurable 16bit Adder using Reversible gates

Dr Abraham Mathew, S.Vyshnavi S.Vyshnavi, SK.Salma SK.Salma +2 more

A reconfigurable 16-bit adder utilizing reversible logic is introduced to enhance both energy efficiency and computational performance. The design integrates Toffoli, Peres, and Haghparast–Navi Gate (HNG) to construct optimized full adder units with lower quantum cost, reduced garbage outputs, and minimal constant inputs. A reversible multiplexer is employed to enable seamless switching between Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA) configurations. While RCA mode supports power-efficient operation, CLA mode enables faster computation, allowing the circuit to adapt to different processing requirements. Performance evaluation is carried out considering propagation delay, power consumption and hardware utilization. The analysis indicates enhanced efficiency over existing reversible adder designs. Due to its adaptable structure and scalable nature, the architecture is appropriate for reversible computing, quantum systems, and low-power VLSI applications.

Technix International Journal for Engineering ResearchJan 1, 20260 citations

A New Design of an N-Bit Reversible Arithmetic Logic Unit

Subhankar Pal, Chetan Kumar Vudadha, P. Sai Phaneendra +2 more

With the advent of nanotechnology, transistors are getting smaller and growing in number according to Moore's Law. With this, the issue of heat dissipation is becoming of greater concern to researchers as the transistor heat dissipation reaches the Land Auer limit. Reversible logic is predicted to be an alternative to conventional computing due to lesser energy dissipation and exponentially faster problem-solving capacity. This paper introduces the design of a reversible ripple-carry adder using a mix of the well-known NCV library and the recently introduced NCV-|v1> library, with the assumption of a four-level quantum system. The results for the proposed adder are compared with previous ripple-carry adder designs. It then explores the design of a cost-optimized reversible ALU by modifying the above adder. Finally, a comparison of the proposed ALU is made with one of the latest reversible ALU designs.

International Symposium on Electronic System DesignDec 1, 20149 citations