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IEEE Transactions on Magnetics

Characteristics of a counter-electrode coupled logic gate using Josephson junctions

S. Hasuo, Hideo Suzuki, Toyoshi Yamaoka

Published Jan 1, 1981• 6 citations
Publisher

Abstract

This paper proposes a new superconducting logic device controlled by input signal currents applied to the counter-electrode of a tunneling junction. This device has no specific control lines unlike the conventional magnetically coupled logic devices. Input signals couple to the junction magnetically by using the counter-electrode instead of the control line. We call this a Counter-electrode Coupled Logic (CCL) gate. The following describes the basic characteristics of the CCL gate.

DOI
10.1109/tmag.1981.1061157

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This paper proposes a new superconducting logic device controlled by input signal currents applied to the counter-electrode of a tunneling junction. This device has no specific control lines unlike the conventional magnetically coupled logic devices. Input signals couple to the junction magnetically by using the counter-electrode instead of the control line. We call this a Counter-electrode Coupled Logic (CCL) gate. The following describes the basic characteristics of the CCL gate.
We present a superconducting logic family whose operation relies on the availability of a current gain greater than one, based on the analogy to semiconductor complementary metal-oxide-semiconductor (CMOS) logic family. The Complementary Josephson Junction (CJJ) logic family utilizes two types of nonlatching devices: a conventional device and a complementary device. The conventional device has a finite critical current, and the complementary device has zero critical current with no input applied. When the input is high, the complementary device has a finite critical current, while the conventional device has zero critical current. The bias current can be steered between a branch with a complementary device and a branch with a conventional device performing logic (and memory) functions. We can also use a resistor as a load to a complementary device. We call this circuit topology the Resistor Complementary Josephson Junction (RCJJ) family. It is analogous to the semiconductor PMOS/resistor logic family. In this paper, we investigate methods of realizing complementary devices, and we present a preliminary analysis of speed, margins, and power dissipation in simple CJJ and RCJJ inverter circuits.
We describe a technique for fabricating magnetically coupled Josephson logic and memory circuits and SQUIDs which uses only two superconducting layers. These two layers perform multiple functions as the base and counterelectrodes of the tunnel junctions, the SQUID inductance and control lines, and the signal lines and groundplane between gates. This technique is illustrated by the specific example of a two junction, resistively damped SQUID designed to be fabricated using an all-refractory process which employs a total of five masking levels.
A Josephson superconducting quantum interference device (SQUID) digital logic family was developed that uses the R/sub nn/ region of a Josephson junction (JJ) to compensate for variations in where R/sub nn/ is the effective resistance of a JJ in the linear I-V region beyond the gap. The basic compensating junction logic (CJL) circuit is two 2-input-OR 1-2-1 interferometer isolators that, when switched, inject current into a 2-input-AND 1-2-1 interferometer. The R/sub nn/ region of several JJs is used in series with a resistor to set the current from the power supply to the 2-input-OR interferometers. The 2-input-AND interferometer is implemented with both current injection and magnetic coupling. The latch circuit uses both current injection and magnetic coupling design techniques to increase the range of I/sub O/, inductance, and resistance variation over which the latch will function correctly. Experimental measurements of CJL circuits are described.>
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We propose non-latching gates based on Superconducting QUantum Interference Device (SQUID) and logic circuits based on it. The gate consists of a 3-junction-SQUID coupled with an RF-SQUID inductively. According to numerical simulation, the wide bias margin reached /spl plusmn/52%. Adopting the magnetic coupling to apply input signals, the fan-out larger than unity was obtained without reducing signal current level. These consequences enabled us to realize complicated logic functions using this gate, The gate delay was 4.5ps at Jc=10kA/cm/sup 2/. An EXOR gate composed of two gates had the bias margin of /spl plusmn/35% and the delay time of 12ps. The operation in non-latching mode is also suitable for digital circuits based on HTS junctions.