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IEEE Transactions on Applied Superconductivity

Junction Yield Analysis for 10 V Programmable Josephson Voltage Standard Devices

Anna E. Fox, Paul D. Dresselhaus, Alain Rüfenacht, Aric W. Sanders, Samuel P. Benz

Published Dec 5, 2014• 34 citations
Publisher

Abstract

Analysis of the Josephson junction yield in the National Institute of Standards and Technology 10 V Programmable Josephson Voltage Standard (PJVS) has been performed by fabricating and measuring over 25 million Nb/NbxSi1-x/Nb junctions. Using the 265 116 junctions per PJVS device, it was possible to measure Shapiro steps on current voltage curves and then estimate the number of single-junction defects within these long arrays. By comparing the results of a quantum-based measurement to a model simulating junction defects, the quantity and magnitude of a small number of junction defects can be estimated from an array of many thousands of junctions. Understanding the source of junction defects in the fabrication process is important for maximizing yield and uniformity, both of which directly relate to the current margin of the quantized voltage step. We have recently fabricated 18 imperfect but usable PJVS devices and 16 that were free from defects, many with n = 1 Shapiro step margins approximately equal to 2 mA. The best of these wafers had a junction defect density of around 3 in a million.

DOI
10.1109/tasc.2014.2377744

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Analysis of the Josephson junction yield in the National Institute of Standards and Technology 10 V Programmable Josephson Voltage Standard (PJVS) has been performed by fabricating and measuring over 25 million Nb/NbxSi1-x/Nb junctions. Using the 265 116 junctions per PJVS device, it was possible to measure Shapiro steps on current voltage curves and then estimate the number of single-junction defects within these long arrays. By comparing the results of a quantum-based measurement to a model simulating junction defects, the quantity and magnitude of a small number of junction defects can be estimated from an array of many thousands of junctions. Understanding the source of junction defects in the fabrication process is important for maximizing yield and uniformity, both of which directly relate to the current margin of the quantized voltage step. We have recently fabricated 18 imperfect but usable PJVS devices and 16 that were free from defects, many with n = 1 Shapiro step margins approximately equal to 2 mA. The best of these wafers had a junction defect density of around 3 in a million.
The design, fabrication, and the characterization of a 0.5-V Josephson junction array device are presented for the quantum voltage standards in the National Institute of Metrology (NIM) of China. The device consists of four junction arrays, each of which has 1200 3-stacked Nb/Nb x Si1−x /Nb junctions and an on-chip superconducting microwave circuit which is mainly a power divider enabling each Josephson array being loaded with an equal amount of microwave power. A direct current (dc) quantum voltage of about 0.5 V with a ∼1-mA current margin of the 1st quantum voltage step is obtained. To further prove the quality of NIM device, a comparison between the NIM device with the National Institute of Standards and Technology (NIST) programmable Josephson voltage standard (PJVS) system device is conducted. The difference of the reproduced 0.5-V quantum voltage between the two devices is about 0.55 nV, which indicates good agreement between the two devices. With the homemade device, we have realized a precise and applicable 0.5-V applicable-level quantum voltage.
A 10-V programmable Josephson voltage standard (PJVS) circuit including 524 288 vertically stacked NbN/TiN/NbN Josephson junctions was successfully fabricated without any defects. The chip was cooled with a compact cryocooler at a temperature of 9.8 K and generated an output voltage of 17.3 V with the first Shapiro step height of 1.0 mA under microwave irradiation at 16 GHz. Furthermore, the circuit design having the high output voltage increased the number of available chips for the 10-V PJVS. The fabrication yield for the chip, which generates greater than 10 V, was 36%, which is ten times greater than that for a perfect chip without any defects. This method was not effective for the chip that had serious defects, such as a disconnection across the array or short between the array and ground; thus, efforts to reduce such defects, e.g., frequent maintenance inside vacuum chambers for film preparation and etching, were found to be essential.
Programmable Josephson voltage standard (PJVS) circuits were developed that operate at 16 GHz to 20 GHz with operating margins larger than 1 mA. Two circuit designs were demonstrated, each having a total of ~ 300,000 junctions, which were divided into either 16 or 32 sub-arrays. Triple-stacked junctions were used in order to fit the ~300,000 junctions on each circuit. The amorphous NbxSi1-x-barrier junction technology provided a high degree of uniformity of the barrier and junction electrical properties, which was necessary to achieve the 1 mA operating margin. Although the margins on both the 16-array and 32-array circuits were much greater than 1 mA, the circuit yield for the 16-array design was lower because the longer arrays are more sensitive to defects. The use of lumped-element microwave splitters and tapered arrays significantly reduced the microwave input power and increased the operating margins of these designs. In addition, the broadband microwave response of the designs allowed the PJVS output voltage to be continuously adjusted by using the microwave frequency while remaining on margins.
A 10 V programmable Josephson voltage standard (PJVS) circuit with a maximum output voltage of 20 V and a microwave bias of 18.5 GHz was designed and fabricated. Although an attempt was made to improve the fabrication yield for the 10 V PJVS circuit, it was not sufficiently large to reproducibly fabricate a perfect chip without any defects. The redundant arrays were additionally integrated to increase the maximum output voltage, which contributed to an increase in the number of available chips under the limited fabrication yield. Fortunately, most of the defective arrays had a zeroth Shapiro step, while the first step was very small or zero. If the array was not dc biased, it did not generate any voltage, because it worked as a superconductive wiring. In this case, the maximum output voltage became smaller than that of a perfect chip, but it functioned as a 10 V PJVS, due to the back-up arrays.
NIST is designing a 10 V Programmable Josephson Voltage Standard (PJVS) system with an improved microwave design and arrays of stacked NbxSi1-x-barrier Josephson junctions. For this new design a "ground-up" approach was used that takes into account all system issues in order to produce a robust 10 V system. By improving the uniformity of the microwave drive along the length of each array, constant-voltage steps with a larger current range are generated allowing the use of smaller critical current junctions. Smaller critical currents are important for lowering the total overall power dissipated on chip. Reducing power dissipation also increases the operating margins. Thus, all aspects of the design are interrelated and important for an optimized system.
524,288 NbN-based Josephson junctions were integrated to produce a programmable Josephson voltage standard (PJVS) on a die of 15mm × 15mm, and the PJVS circuit was cooled to 10K using a cryocooler and operated with a current margin of about 1.0mA. Although an output voltage of 10V was required for a voltage standard, the circuit was designed to generate the maximum output voltage of 17V because it was difficult to avoid a reduction of the output voltage due to defects. Although a perfect chip without any defect was rarely fabricated, the high voltage chip that generated at least 10V was fabricated with the fabrication yield of larger than 30%. The fabrication yield was also improved by optimizing the film growth conditions to reduce the film stress and the number of particles. Applications for a secondary voltage standard and an ac Josephson voltage standard are also described.