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IEEE Transactions on Applied Superconductivity

10 Volt Programmable Josephson Voltage Standard Circuits Using NbSi-Barrier Junctions

Paul D. Dresselhaus, Michael M. Elsbury, David I. Olaya, Charles J. Burroughs, Samuel P. Benz

Published Nov 9, 2010• 59 citations
Publisher

Abstract

Programmable Josephson voltage standard (PJVS) circuits were developed that operate at 16 GHz to 20 GHz with operating margins larger than 1 mA. Two circuit designs were demonstrated, each having a total of ~ 300,000 junctions, which were divided into either 16 or 32 sub-arrays. Triple-stacked junctions were used in order to fit the ~300,000 junctions on each circuit. The amorphous NbxSi1-x-barrier junction technology provided a high degree of uniformity of the barrier and junction electrical properties, which was necessary to achieve the 1 mA operating margin. Although the margins on both the 16-array and 32-array circuits were much greater than 1 mA, the circuit yield for the 16-array design was lower because the longer arrays are more sensitive to defects. The use of lumped-element microwave splitters and tapered arrays significantly reduced the microwave input power and increased the operating margins of these designs. In addition, the broadband microwave response of the designs allowed the PJVS output voltage to be continuously adjusted by using the microwave frequency while remaining on margins.

DOI
10.1109/tasc.2010.2079310

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Programmable Josephson voltage standard (PJVS) circuits were developed that operate at 16 GHz to 20 GHz with operating margins larger than 1 mA. Two circuit designs were demonstrated, each having a total of ~ 300,000 junctions, which were divided into either 16 or 32 sub-arrays. Triple-stacked junctions were used in order to fit the ~300,000 junctions on each circuit. The amorphous NbxSi1-x-barrier junction technology provided a high degree of uniformity of the barrier and junction electrical properties, which was necessary to achieve the 1 mA operating margin. Although the margins on both the 16-array and 32-array circuits were much greater than 1 mA, the circuit yield for the 16-array design was lower because the longer arrays are more sensitive to defects. The use of lumped-element microwave splitters and tapered arrays significantly reduced the microwave input power and increased the operating margins of these designs. In addition, the broadband microwave response of the designs allowed the PJVS output voltage to be continuously adjusted by using the microwave frequency while remaining on margins.
At Physikalisch-Technische Bundesanstalt (PTB), superconducting 10 V circuits for the programmable Josephson voltage standard (PJVS) are routinely manufactured on the basis of NbxSi1-x barrier junctions. This paper describes in detail the basic design principles for an operating frequency of 70 GHz. It starts with single junctions, discusses their insertion into microstriplines and closes with the whole microwave circuit containing 69,632 NbxSi1-x barrier junctions arranged over 128 microstriplines connected in parallel. The microwave attenuation of this junction type is a key parameter for the 10 V design and we report its experimental determination. Special attention has been devoted to subarrays with just a few Josephson junctions in one of the outermost striplines. The arrangement of these subarrays determines the optimum performance of the complete 10 V series array. The high performance of programmable 10 V circuits fabricated at PTB is characterized by measured operating margins in all subarrays of more than 1 mA centered at the same dc bias current. The observed modulation of the current margins, when changing the frequency around 70 GHz, is explained by microwave reflections caused by the rf waveguide inside the cryoprobe. We determine the current margins in dependence of the output power of a microwave synthesizer and show that 60 mW is sufficient to achieve current margins larger than 1 mA.
NIST is designing a 10 V Programmable Josephson Voltage Standard (PJVS) system with an improved microwave design and arrays of stacked NbxSi1-x-barrier Josephson junctions. For this new design a "ground-up" approach was used that takes into account all system issues in order to produce a robust 10 V system. By improving the uniformity of the microwave drive along the length of each array, constant-voltage steps with a larger current range are generated allowing the use of smaller critical current junctions. Smaller critical currents are important for lowering the total overall power dissipated on chip. Reducing power dissipation also increases the operating margins. Thus, all aspects of the design are interrelated and important for an optimized system.
Programmable Josephson voltage standard (PJVS) circuits using arrays of NbN/TiN/NbN/TiN/NbN double-junction stacks were fabricated and operated at a temperature of 10 K. Four arrays each with 32 768 junctions produced expected voltage outputs when driven at (10, 15, 17, and 20) GHz with an operating current range of 0.2-1.0 mA. Another circuit showed constant-voltage steps at /spl plusmn/6 V when driven with an 11 GHz microwave bias, indicating that over 260 000 junctions were operating properly. This circuit did not show constant-voltage steps when driven with a 19 GHz microwave bias, which was the design frequency to achieve /spl plusmn/10 V output voltage.
PTB started using the robust NbxSi1-xbarrier junction technology for the fabrication of large arrays for the Programmable Josephson Voltage Standard (PJVS) and for the Josephson Arbitrary Waveform Synthesizer 3 years ago. We demonstrate how Nb-doping of the amorphous Si barrier causes the transition from an underdamped to a desired overdamped junction behavior. Special dc SQUIDs have been used to evaluate junction capacitance and noise properties. The critical current of small junctions as a function of applied magnetic field has been investigated. On the basis of an existing 70 GHz design previously used for 10 V PJVS chips, we fabricated for the first time 20 V circuits with nearly 140 000 double-stacked Josephson junctions. A direct on-chip comparison between the two 10 V halves of the binary-divided array confirmed the metrological suitability of the 20 V circuits for dc and ac applications.
A 10-V programmable Josephson voltage standard (PJVS) circuit including 524 288 vertically stacked NbN/TiN/NbN Josephson junctions was successfully fabricated without any defects. The chip was cooled with a compact cryocooler at a temperature of 9.8 K and generated an output voltage of 17.3 V with the first Shapiro step height of 1.0 mA under microwave irradiation at 16 GHz. Furthermore, the circuit design having the high output voltage increased the number of available chips for the 10-V PJVS. The fabrication yield for the chip, which generates greater than 10 V, was 36%, which is ten times greater than that for a perfect chip without any defects. This method was not effective for the chip that had serious defects, such as a disconnection across the array or short between the array and ground; thus, efforts to reduce such defects, e.g., frequent maintenance inside vacuum chambers for film preparation and etching, were found to be essential.
A 10 V programmable Josephson voltage standard (PJVS) circuit with a maximum output voltage of 20 V and a microwave bias of 18.5 GHz was designed and fabricated. Although an attempt was made to improve the fabrication yield for the 10 V PJVS circuit, it was not sufficiently large to reproducibly fabricate a perfect chip without any defects. The redundant arrays were additionally integrated to increase the maximum output voltage, which contributed to an increase in the number of available chips under the limited fabrication yield. Fortunately, most of the defective arrays had a zeroth Shapiro step, while the first step was very small or zero. If the array was not dc biased, it did not generate any voltage, because it worked as a superconductive wiring. In this case, the maximum output voltage became smaller than that of a perfect chip, but it functioned as a 10 V PJVS, due to the back-up arrays.