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IEEE Transactions on Magnetics

Nondestructive memory cell using a two-junction Josephson interferometer

Michitada Morisue, S. Koike, K. Moritan

Published May 1, 1983• 0 citations
Publisher

Abstract

This paper presents a novel nondestructive memory cell using a two-junction interferometer. Most of single-flux-quantum memory cells have been the destructive ones, which must rewrite the information for logic "1" after a reading operation. This makes the circuitry of the cell complex. To avoid this disadvantage, a novel self-rewriting technique is introduced by setting a coil between the terminals of the interferometer. The principle of the operation of the cell is described and the simulation for the behaviours of the cell are illustrated in detail. The results of the simulation show that the reliable operation of the cell can be achieved with high operating speed.

DOI
10.1109/tmag.1983.1062386

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This paper proposes a novel associative memory circuit using Josephson interferometers. This associative memory circuit is mainly constructed with the nondestructive memory cell in which a self-rewriting operation can be achieved by setting a coil between the terminals of the interferometer. The principle of the associative memory circuit is described and the results of simulation for the operation are illustrated. The results show that the cycle time of operation is less than 75ps and the design tolerance of input signals for the memory circuit is about 8%.
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A proposal vortex transitional nondestructive read-out Josephson memory cell is successfully fabricated and tested. The memory cell consists of two superconducting loops in which a single flux quantum is stored and a two-junction interferometer gate as a sense gate. The memory cell employs vortex transitions in the superconducting loops for writing and reading data. The vortex transitional memory operation of the cell contributes to improving its sense discrimination and operating margin. The memory cell is activated by two control signals without timing control signals. Memory cell chips have been fabricated using a niobium planarization process. A±21% address signal current margin and a ±33% sense gate current margin have been obtained experimentally. Successful memory operations of a cell driven by two-junction interferometer gates has been demonstrated. The single flux quantum operations of this memory cell makes it an attractive basic element for a high-speed cache memory.
In single flux quantum interferometer memory cells the information can be stored without bias current, if the interferometer inductance L is chosen sufficiently large (\lambda = 2\piLI_{0}/\Phi_{0} = 2\pi) to allow for three stable states (-1-, 0-, 1-mode) at zero control and gate current. In this case the binary informations are represented by the -1- and 0-mode of the interferometer. The nondestructive read out operation of a binary "1" is performed without a transition into another mode or into the voltage state. The binary "1" corresponds to no sense signal. Nondestructive read out of the binary "0" is achieved in switching to the voltage state and in returning to the 0-mode after the end of the drive currents. In this paper the dynamics of switching back into the zero voltage state are investigated by simulations of trajectories in the order parameter phase plane. It is shown that for realistic fabrication tolerances the interferometer settles in the wanted 0-mode and not in the -1- or 1-mode even under severe gate or control current disturbs, if the maximum Josephson currents of the two Josephson junctions are unequal (2:1) and if the McCumber damping factor is sufficiently large (\beta \approx 100).
A new vortex transitional NDRO memory cell has been proposed for use as a high-speed cache memory. The memory cell consists of two superconducting loops with one Josephson junction and a two-junction interferometer gate. The superconducting loop stores single-flux quantum. The interferometer gate operates as a sense gate. The memory cell employs a vortex transition in the superconducting loop for the writing and reading of data. The sense gate current margin increases to ±38% since the coupling magnetic flux is amplified by the vortex transition for nominally designed cell parameters. The memory cell operates with a ±33% address signal current margin. This paper describes the memory cell design and the dynamic behavior of computer simulations.