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Superconductor Science and Technology

Design and high-speed test of (4 × 8)-bit single-flux-quantum shift register files

K. Fujiwara, Y Yamashiro, Nobuyuki Yoshikawa, Akira Fujimaki, Hirotaka Terai, Shinichi Yorozu

Published Nov 5, 2003• 12 citations
Publisher

Abstract

In the realization of large-scale single-flux-quantum (SFQ) digital systems, one of the most serious problems is the lack of high-density and high-speed memories. We have been developing random access memories using SFQ shift registers, which are one candidate to solve the memory problem in the SFQ digital system because of their high throughput and short access time. In this paper we have designed and tested a (4 × 8)-bit SFQ shift register file as a demonstration of the SFQ shift register memory system. Its target clock frequency is 20 GHz assuming an NEC 2.5 kA cm −2 Nb standard process. In the test, we have confirmed that 8-bit dual-rail data can be loaded to appropriate shift registers specified by 2-bit address data. We have also verified that the loaded data are read out and written back to the same shift register at high speed. A tested dc bias margin at 20 GHz is ±5%.

DOI
10.1088/0953-2048/16/12/030

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IEEE Transactions on Applied Superconductivity•Jun 1, 2003•34 citations
In the realization of large-scale single-flux-quantum (SFQ) digital systems, one of the most serious problems is the lack of high-density and high-speed memories. We have been developing random access memories using SFQ shift registers, which are one candidate to solve the memory problem in the SFQ digital system because of their high throughput and short access time. In this paper we have designed and tested a (4 × 8)-bit SFQ shift register file as a demonstration of the SFQ shift register memory system. Its target clock frequency is 20 GHz assuming an NEC 2.5 kA cm −2 Nb standard process. In the test, we have confirmed that 8-bit dual-rail data can be loaded to appropriate shift registers specified by 2-bit address data. We have also verified that the loaded data are read out and written back to the same shift register at high speed. A tested dc bias margin at 20 GHz is ±5%.
The lack of a high-density and high-speed memory is a serious impediment for realization of large-scale RSFQ digital systems. A shift resister memory, which has high throughput and simple circuit structure, is one candidate to overcome this drawback. We show a design framework of the shift register memory, which is usable for the high-speed register files and the main memories of the RSFQ microprocessor. The proposed system consists of an array of shift registers and a packet decoder that switches a high-speed serial data stream into the specified shift register. The target clock frequency is 16 GHz assuming 2.5 kA/cm/sup 2/ Nb standard process. We have estimated the propagation delay and the circuit area of the data-driven self-timed (DDST) packet decoder. Based on this estimation, we have also evaluated the access time and the area of the memory system. Several key components, including the one-to-two packet switch and the one-to-four DDST packet decoder, were implemented and their correct operations were confirmed.
Abstract In this paper, a shift register (SR) memory based on rapid single flux quantum (RSFQ) logic for bit-parallel access is proposed. The memory cell changes from a row in the memory array to a column to increase the bit of data accessed per one clock cycle. The design of the 8 bit × 2 bit (8 × 2) memory is introduced. The memory consists of four parts: a SR memory array, an input buffer, an output buffer, and a controller, in which the controller is used to produce a control signal at a certain clock cycle specified by the address data. We have obtained the low speed test of the 8 × 2 memory fabricated by 6 kA cm −2 Nb process (SIMIT-Nb03), all bit-parallel access operations (write, read, clear and write, and read again) have been verified. We also simulated the 8 × 8 memory with data width expansion and obtained the maximum operating frequency of 34 GHz after the place and route with the SIMIT-Nb03 cell library. Based on the hierarchical storage, we have used the 8 × 8 memory as a basic block to construct large size of memory system, the access time and bandwidth have been evaluated. The bit-parallel memory shows higher bandwidth than bit-serial memory with the same capacity, especially for large capacity memory.
Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm −2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters β c of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.
Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of +or-23% and +or-14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO/sub x//Nb process with a junction critical current density of 1.0 kA/cm/sup 2/.>
Error rates of rapid-single-flux-quantum (RSFQ) shift register memories were investigated using a high-speed error-rate measurement system in order to demonstrate their reliability and stability. We designed and implemented an 8 times 8-bit shift register memory using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The total number of Josephson junctions including the test system is 4184, and the circuit area is 2.1 mm times 3.2 mm. We measured the error rates of every storage node by reading out the data 216times at the clock frequency of 16 GHz. The measured error rates were lower than 10-10with DC bias margin better than plusmn5%.
An eight-bit SFQ processor has been designed and some key components have been tested to confirm feasibility of the large-scale SFQ digital circuit. The designed processor is composed of a one-bit ALU, two eight-bit registers with local clock generators, an instruction register, a five-bit program counter, a state controller, and a 32-byte register file. A bit-serial architecture and a distributed local clock architecture, where each register has its own local clock generator, have been employed in order to increase the local clock frequency. The target clock frequency is 16 GHz and 10 GHz for the NEC 2.5 kA/cm/sup 2/ and Hypres 1 kA/cm/sup 2/ Nb processes. On the circuit design level, we have used a data-driven self-timed architecture and a binary decision diagram, which reduce the timing design difficulty in high frequency operation. The processor, which contains 7,300 Josephson junctions, has been designed by using a cell-based design methodology with the assistance of a top-down CAD environment. We have successfully tested some important circuit blocks, including a one-bit ALU, eight-bit registers, and a demultiplexer for register files.