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Bulletin of the American Physical Society

Coherent electron spin transport and fault-tolerant semiconductor-based quantum computer architectures.

Lloyd C. L. Hollenberg

Published Mar 7, 2007• 0 citations
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Solid state quantum computer architectures are often touted as inherently scalable on the basis of proven classical architecture miniaturisation - i.e. through sheer ease of component replication. However, this weak scaling argument misses the vast complexity of the implementation of fault-tolerant quantum protocols required to protect quantum information processing against errors. In a successful design of strongly scalable quantum computer architecture, highly non-trivial requirements such as qubit transport, logic gates for physically separated qubits, fast read-out and resources for classical processing and error correction must be incorporated. We review a new adiabatic scheme coherent (spin) transport by adiabatic passage (CTAP) for physical qubit transport particularly suited to atomic and solid-state systems. The tunnelling rates, transfer times and the effects of decoherence are calculated for CTAP using phosphorous donors in silicon. Using CTAP qubit transport we have proposed a bi-linear donor electron spin architecture with potential for scale-up to fault-tolerant operation. This architecture allows for the distribution of interaction, storage and readout regions and incorporates non-nearest-neighbour interactions between qubits. The transport rails which provide these non-local interactions, also provide alternative pathways to avoid non-functioning regions. The key questions under investigation are whether one can: perform fault-tolerant quantum computation on such an architecture, and determine quantitative estimates of the fault-tolerant threshold.

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Solid state quantum computer architectures are often touted as inherently scalable on the basis of proven classical architecture miniaturisation - i.e. through sheer ease of component replication. However, this weak scaling argument misses the vast complexity of the implementation of fault-tolerant quantum protocols required to protect quantum information processing against errors. In a successful design of strongly scalable quantum computer architecture, highly non-trivial requirements such as qubit transport, logic gates for physically separated qubits, fast read-out and resources for classical processing and error correction must be incorporated. We review a new adiabatic scheme coherent (spin) transport by adiabatic passage (CTAP) for physical qubit transport particularly suited to atomic and solid-state systems. The tunnelling rates, transfer times and the effects of decoherence are calculated for CTAP using phosphorous donors in silicon. Using CTAP qubit transport we have proposed a bi-linear donor electron spin architecture with potential for scale-up to fault-tolerant operation. This architecture allows for the distribution of interaction, storage and readout regions and incorporates non-nearest-neighbour interactions between qubits. The transport rails which provide these non-local interactions, also provide alternative pathways to avoid non-functioning regions. The key questions under investigation are whether one can: perform fault-tolerant quantum computation on such an architecture, and determine quantitative estimates of the fault-tolerant threshold.
Spin qubits in silicon quantum dot arrays are a promising quantum computation platform for long-term scalability due to their small qubit footprint and compatibility with advanced semiconductor manufacturing. However, spin qubit devices face a key architectural bottleneck: the large physical footprint of readout components relative to qubits prevents a dense layout where all qubits can be measured simultaneously, complicating the implementation of quantum error correction. This challenge is offset by the platform's unique rapid shuttling capability, which can be used to transport qubits to distant readout ports. In this work, we explore the design constraints and capabilities of spin qubits in silicon and propose the SNAQ (Shuttling-capable Narrow Array of spin Qubits) surface code architecture, which relaxes the 1:1 readout-to-qubit assumption by leveraging spin shuttling to time-multiplex ancilla qubit initialization and readout. Our analysis shows that, given sufficiently high (experimentally demonstrated) qubit coherence times, SNAQ delivers an orders-of-magnitude reduction in chip area per logical qubit. Additionally, by using a denser grid of physical qubits, SNAQ enables fast transversal logic for short-distance logical operations, achieving over 10x improvement in local logical clock speed while still supporting global operations via lattice surgery. This translates to a 3.2-5.7x improvement in key Adder and Lookup fault-tolerant subroutines. Our work pinpoints critical hardware metrics and provides a compelling path toward high-performance fault-tolerant computation on near-term-manufacturable spin qubit arrays.