Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

European Wireless Conference

Forced Convergence Decoding of LDPC Codes - EXIT Chart Analysis and Combination with Node Complexity Reduction Techniques

Ernesto Zimmermann, Wolfgang Rave, Gerhard Paul Fettweis

Published Apr 10, 2005• 24 citations
OpenAlex

Abstract

Abstract: Recently, the concept of forced convergence decoding for Low-Density Parity-Check Codes has been introduced. Restricting the message passing in the iterative process to the nodes that still significantly contribute to the decoding result, this approach allows for substantial reduction in decoding complexity at negligible deterioration in performance. We analyze this novel technique using EXIT charts and show how it compares to and can be combined with other complexity reduction techniques. Our findings imply that forced convergence works effectively in conjunction with other complexity reduction techniques while retaining its attractiveness in terms of the complexity-performance trade-off. 1

Related papers

Reduced Complexity LDPC Decoding using Forced Convergence

Ernesto Zimmermann, Gerhard Paul Fettweis, Prakash Pattisapu +1 more

Abstract — Low-density parity-check (LDPC) codes have recently emerged as a viable option for forward error correction (FEC) in future wireless communications systems. One factor influencing the decision of whether to use a specific FEC technique in a system is its suitability for real time systems – and hence, its computational complexity. In this paper, we present a novel LDPC decoding architecture, where we use a threshold rule to decide whether a variable node of the LDPC decoder should update its information in subsequent iterations of the decoding process, or be considered as converged. We show that by choosing this threshold appropriately, decoding complexity can be significantly reduced with only negligible deterioration in error correction performance. I.

•Jan 1, 2004•51 citations

Fast convergence algorithm for decoding of low density parity check codes

Jin Xie, Liuguo Yin, Ning Ge +1 more

Abstract: In this paper, a fast-convergence algorithm is proposed for the decoding of low-density parity-check (LDPC) codes. By putting more weight on the message update from check node to variable node in current iteration, the proposed method speeds up the decoding significantly. Simulation results show that compared with the standard layered min-sum decoding algorithm, the proposed scheme may reduce about 1/6 iteration numbers for LDPC codes used in DVB-S2, with hardware complexity overhead less than 2%. Key–Words: LDPC code, fast convergence decoding algorithm, layered decoding, min-sum algorithm, hardware implementation 1

WSEAS TRANSACTIONS on COMMUNICATIONS archive•Jul 1, 2009•1 citation

A hybrid low complexity decoding of LDPC codes

Hua Wang, Guangrong Fan, Jingming Kuang

An efficient early stopping criterion based on the evolution of the number of reliable variable nodes (NRVN) is proposed for low density parity check (LDPC) codes in this paper. This criterion can significantly reduce the average number of iterations (ANI) at low to middle signal to noise ratios (SNRs) with minimal performance degradation. Furthermore, a hybrid decoding method is presented to reduce the decoding complexity of LDPC codes by combining the proposed stopping criterion and forced convergence (FC) decoding algorithm. Compared with the classic belief propagation (BP) decoding, significant computation complexity reduction can be achieved with small computation overhead.

IET International Conference on Wireless, Mobile and Multimedia Networks (ICWMMN)•Jan 1, 2010•1 citation

Convergence Analysis of Iterative Threshold Decoding Process

Mohammed Lahmer, Mostafa Belkasmi, Abdallah Rhattoy

Today the error correcting codes are present in all the telecom standards, in particular the low density parity check (LDPC) codes. The choice of a good code for a given network is essentially linked to the decoding performance obtained by the bit error rate (BER) curves. This approach requires a significant simulation time proportional to the length of the code, to overcome this problem Exit chart was introduced, as a fast technique to predict the performance of a particular class of codes called Turbo codes. In this paper, we success to apply Exit chart to analyze convergence behavior of iterative threshold decoding of one step majority logic decodable (OSMLD) codes. The iterative decoding process uses a soft-input soft-output threshold decoding algorithm as component decoder. Simulation results for iterative decoding of simple and concatenated codes transmitted over a Gaussian channel have shown that the thresholds obtained are a good indicator of the Bit Error Rate (BER) curves.

Journal of Computer and Communications•Jan 1, 2016•1 citation

Efficient Analysis, Design and Decoding of Low-Density Parity-Check Codes

Masoud Ardakani

This dissertation presents new methods for the analysis, design and decoding of low-density parity-check (LDPC) codes. We start by studying the simplest class of decoders: the binary message-passing (BMP) decoders. We show that the optimum BMP decoder must satisfy certain symmetry and isotropy conditions, and prove that Gallager's Algorithm B is the optimum BMP algorithm. We use a generalization of extrinsic information transfer (EXIT) charts to formulate a linear program that leads to the design of highly efficient irregular LDPC codes for the BMP decoder. We extend this approach to the design of irregular LDPC codes for the additive white Gaussian noise channel. We introduce a "semi-Gaussian" approximation that very accurately predicts the behaviour of the decoder and permits code design over a wider range of rates and code parameters than in previous approaches. We then study the EXIT chart properties of the highest rate LDPC code which guarantees a certain convergence behaviour. We also introduce and analyze gear-shift decoding in which the decoder is permitted to select the decoding rule from among a predefined set. We show that this flexibility can give rise to significant reductions in decoding complexity. Finally, we show that binary LDPC codes can be combined with quadrature amplitude modulation to achieve near-capacity performance in a multitone system over frequency selective Gaussian channels.

•Jan 1, 2004•14 citations

Reduced-Complexity Decoding of LDPC Codes

Reduced-Complexity Decoding of LDPC Codes Various log-likelihood-ratio-based belief-propagation (LLR- BP) decoding algorithms and their reduced-complexity derivatives for low-density parity-check (LDPC) codes are presented. Numerically accurate representations of the check-node update computation used in LLR-BP decoding are described. Furthermore, approximate representation of the decoding computations are shown to achieve a reduction in complexity, by simplifying the check-node update or symbol-node update, or both. In particular, two main approaches for simplified check-node updates are presented that are based on the so-called min-sum approximation coupled with either a normalization term or an additive offset term. Density evolution is used to analyze the performance of these decoding algorithms, to determine the optimum values of the key parameters, and to evaluate finite quantization effects. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of the BP algorithm. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from a performance, latency, computational complexity, and memory-requirement perspective.

IEEE Transactions on Communications•Jul 1, 2005•27 citations
Abstract: Recently, the concept of forced convergence decoding for Low-Density Parity-Check Codes has been introduced. Restricting the message passing in the iterative process to the nodes that still significantly contribute to the decoding result, this approach allows for substantial reduction in decoding complexity at negligible deterioration in performance. We analyze this novel technique using EXIT charts and show how it compares to and can be combined with other complexity reduction techniques. Our findings imply that forced convergence works effectively in conjunction with other complexity reduction techniques while retaining its attractiveness in terms of the complexity-performance trade-off. 1
Abstract — Low-density parity-check (LDPC) codes have recently emerged as a viable option for forward error correction (FEC) in future wireless communications systems. One factor influencing the decision of whether to use a specific FEC technique in a system is its suitability for real time systems – and hence, its computational complexity. In this paper, we present a novel LDPC decoding architecture, where we use a threshold rule to decide whether a variable node of the LDPC decoder should update its information in subsequent iterations of the decoding process, or be considered as converged. We show that by choosing this threshold appropriately, decoding complexity can be significantly reduced with only negligible deterioration in error correction performance. I.
Abstract: In this paper, a fast-convergence algorithm is proposed for the decoding of low-density parity-check (LDPC) codes. By putting more weight on the message update from check node to variable node in current iteration, the proposed method speeds up the decoding significantly. Simulation results show that compared with the standard layered min-sum decoding algorithm, the proposed scheme may reduce about 1/6 iteration numbers for LDPC codes used in DVB-S2, with hardware complexity overhead less than 2%. Key–Words: LDPC code, fast convergence decoding algorithm, layered decoding, min-sum algorithm, hardware implementation 1
An efficient early stopping criterion based on the evolution of the number of reliable variable nodes (NRVN) is proposed for low density parity check (LDPC) codes in this paper. This criterion can significantly reduce the average number of iterations (ANI) at low to middle signal to noise ratios (SNRs) with minimal performance degradation. Furthermore, a hybrid decoding method is presented to reduce the decoding complexity of LDPC codes by combining the proposed stopping criterion and forced convergence (FC) decoding algorithm. Compared with the classic belief propagation (BP) decoding, significant computation complexity reduction can be achieved with small computation overhead.
Today the error correcting codes are present in all the telecom standards, in particular the low density parity check (LDPC) codes. The choice of a good code for a given network is essentially linked to the decoding performance obtained by the bit error rate (BER) curves. This approach requires a significant simulation time proportional to the length of the code, to overcome this problem Exit chart was introduced, as a fast technique to predict the performance of a particular class of codes called Turbo codes. In this paper, we success to apply Exit chart to analyze convergence behavior of iterative threshold decoding of one step majority logic decodable (OSMLD) codes. The iterative decoding process uses a soft-input soft-output threshold decoding algorithm as component decoder. Simulation results for iterative decoding of simple and concatenated codes transmitted over a Gaussian channel have shown that the thresholds obtained are a good indicator of the Bit Error Rate (BER) curves.
This dissertation presents new methods for the analysis, design and decoding of low-density parity-check (LDPC) codes. We start by studying the simplest class of decoders: the binary message-passing (BMP) decoders. We show that the optimum BMP decoder must satisfy certain symmetry and isotropy conditions, and prove that Gallager's Algorithm B is the optimum BMP algorithm. We use a generalization of extrinsic information transfer (EXIT) charts to formulate a linear program that leads to the design of highly efficient irregular LDPC codes for the BMP decoder. We extend this approach to the design of irregular LDPC codes for the additive white Gaussian noise channel. We introduce a "semi-Gaussian" approximation that very accurately predicts the behaviour of the decoder and permits code design over a wider range of rates and code parameters than in previous approaches. We then study the EXIT chart properties of the highest rate LDPC code which guarantees a certain convergence behaviour. We also introduce and analyze gear-shift decoding in which the decoder is permitted to select the decoding rule from among a predefined set. We show that this flexibility can give rise to significant reductions in decoding complexity. Finally, we show that binary LDPC codes can be combined with quadrature amplitude modulation to achieve near-capacity performance in a multitone system over frequency selective Gaussian channels.
Reduced-Complexity Decoding of LDPC Codes Various log-likelihood-ratio-based belief-propagation (LLR- BP) decoding algorithms and their reduced-complexity derivatives for low-density parity-check (LDPC) codes are presented. Numerically accurate representations of the check-node update computation used in LLR-BP decoding are described. Furthermore, approximate representation of the decoding computations are shown to achieve a reduction in complexity, by simplifying the check-node update or symbol-node update, or both. In particular, two main approaches for simplified check-node updates are presented that are based on the so-called min-sum approximation coupled with either a normalization term or an additive offset term. Density evolution is used to analyze the performance of these decoding algorithms, to determine the optimum values of the key parameters, and to evaluate finite quantization effects. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of the BP algorithm. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from a performance, latency, computational complexity, and memory-requirement perspective.