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Reduced Complexity LDPC Decoding using Forced Convergence

Ernesto Zimmermann, Gerhard Paul Fettweis, Prakash Pattisapu, Prabin Kumar Bora

Published Jan 1, 2004• 51 citations
OpenAlex

Abstract

Abstract — Low-density parity-check (LDPC) codes have recently emerged as a viable option for forward error correction (FEC) in future wireless communications systems. One factor influencing the decision of whether to use a specific FEC technique in a system is its suitability for real time systems – and hence, its computational complexity. In this paper, we present a novel LDPC decoding architecture, where we use a threshold rule to decide whether a variable node of the LDPC decoder should update its information in subsequent iterations of the decoding process, or be considered as converged. We show that by choosing this threshold appropriately, decoding complexity can be significantly reduced with only negligible deterioration in error correction performance. I.

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An improvement of the forced-convergence decoding algorithm is discussed. Iterative decoding schemes such as the sum-product (SP) decoding bring out excellent performance of low-density parity check (LDPC) codes. The forced-convergence (FC) decoding is also an iterative decoding algorithm obtained by modifying the SP decoding. The FC decoding succeeds to reduce the decoding complexity of the SP decoding, but the error correcting performance is severely degraded by the modification. The performance degradation of the FC decoding is expected to be mitigated if the convergence criterion used in the algorithm is appropriately modified. This paper discusses several types of modifications of the convergence criteria. Computer simulation shows that the proposed modifications improve the performance of the FC decoding algorithm.

International Symposium on Information Theory and its Applications•Dec 1, 2008•8 citations
Abstract — Low-density parity-check (LDPC) codes have recently emerged as a viable option for forward error correction (FEC) in future wireless communications systems. One factor influencing the decision of whether to use a specific FEC technique in a system is its suitability for real time systems – and hence, its computational complexity. In this paper, we present a novel LDPC decoding architecture, where we use a threshold rule to decide whether a variable node of the LDPC decoder should update its information in subsequent iterations of the decoding process, or be considered as converged. We show that by choosing this threshold appropriately, decoding complexity can be significantly reduced with only negligible deterioration in error correction performance. I.
Abstract: Recently, the concept of forced convergence decoding for Low-Density Parity-Check Codes has been introduced. Restricting the message passing in the iterative process to the nodes that still significantly contribute to the decoding result, this approach allows for substantial reduction in decoding complexity at negligible deterioration in performance. We analyze this novel technique using EXIT charts and show how it compares to and can be combined with other complexity reduction techniques. Our findings imply that forced convergence works effectively in conjunction with other complexity reduction techniques while retaining its attractiveness in terms of the complexity-performance trade-off. 1
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts when the code length is moderate. Check node processing is one bottleneck in NB-LDPC decoding. Various techniques have been proposed to simplify the check node processing. Particularly, the computation complexity can be reduced by employing an iterative forward-backward scheme. However, this scheme requires large memory to store intermediate results. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the Min-max NB-LDPC decoding. The proposed scheme first chooses a limited number of variable-to-check messages, then the check-to-variable messages to all connected variable nodes are generated independently. Employing the proposed architecture, the area requirement of the check node processing for an (837, 726) NB-LDPC code over GF (25) can be reduced to 22.5% of that of the previous work with the same processing speed and error-correcting performance.
Low-density parity-check (LDPC) codes are capacity approaching codes that have rapidly been adopted in modern systems such as the IEEE 802.11n and long term evolution advanced (LTE-A) communications standards. The decoders based on the iterative belief propagation offer exceedingly high performance but unfortunately have high computational complexity. Therefore significant research has focused on lower complexity architectures based on the family of so-called bit-flipping algorithms. In the basic bit-flipping algorithm the number of failed parity checks for each bit is calculated and the sign of the bit with the maximum failed checks is inverted. Inverting bits above a certain threshold removes the complexity of calculating a maximum function and adaptive thresholds on each bit further simplifies the design. The choice of threshold updates directly affects the error and convergence performances. Here we describe a simple architecture that has two decoders with different scaling factors and select the branch with the lowest syndrome sum. It is shown that the addition of a random uniform perturbation to the threshold can reduce the average iteration count further by providing an escape from stuck decoding states.
This paper proposes a simplified forced-convergence (SFC) algorithm to reduce the computational complexity for low-density parity-check (LDPC) decoding. To reduce the computational complexity, the proposed algorithm uses the modified check node (CN) operation that does not use a condition for deactivating CNs. Therefore, the proposed SFC algorithm uses only one threshold value while the existing forced-convergence (FC) algorithm uses two threshold values. The simulation results show that SFC achieves a bit error rate (BER) performance close to min-sum (MS) algorithm. SFC can reduce the computational complexity of check node by approximately 22.21% compared to FC.
In recent years, the demand for low latency and high reliability in industrial have been increasing rapidly. To meet these requirements, we propose a new decoding architecture of low-density parity-check convolutional codes (LDPC-CC). The proposed decoding architecture reduces the distance of the neighboring processors by using the rationale of compact pipeline decoder. At the same time, the stopping rule is employed in the process of iteration and the weighting factor is added to reduce the error propagation caused by the update of the parity-check node, thus accelerating the convergence of the decoding. The results show that the proposed algorithm has about 0.3 dB gain compared with the on-demand variable node activation (OVA) algorithm when the bit rate error (BER) is 10-4and maximum number of iterations is 10. Meanwhile, the initial delay and storage requirement are reduced by about 50% and the average number of iterations per decoded bit is also reduced largely.
An improvement of the forced-convergence decoding algorithm is discussed. Iterative decoding schemes such as the sum-product (SP) decoding bring out excellent performance of low-density parity check (LDPC) codes. The forced-convergence (FC) decoding is also an iterative decoding algorithm obtained by modifying the SP decoding. The FC decoding succeeds to reduce the decoding complexity of the SP decoding, but the error correcting performance is severely degraded by the modification. The performance degradation of the FC decoding is expected to be mitigated if the convergence criterion used in the algorithm is appropriately modified. This paper discusses several types of modifications of the convergence criteria. Computer simulation shows that the proposed modifications improve the performance of the FC decoding algorithm.