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Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

Femtojoule Josephson logic gates

Dennis Herrell

Published Jan 1, 1974• 6 citations
Publisher

Abstract

A JOSEPHSON TUNNELING junction, with a supply current of I,, and having three overlaying input lines to control the maximum supercurrent forms the basis of a logic gate’ ; Figure l(a). The Josephson junction drives a transmission line matched at its far end by a resistor R.
DOI
10.1109/isscc.1974.1155290

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The design and experimental investigation of a simple logic circuit employing Josephson tunnel junctions as the switching elements is described. The design utilized matched transmission lines as signal carriers. The physical layout was simulated on a computer with a model consisting of 3 Josephson gates and 28 transmission line segments. Results of both quasi-static and high speed testing were found to be in essential agreement with theoretical expectations; only dynamic results are presented here in detail. The experimental circuit had gates with 165 ps risetimes, and in the high speed investigation, was operated with bursts of 700 ps risetime pulses tightly spaced so as to simulate a repetition rate of ∼1 GHz.
A quantum-flux-type logic circuit is proposed which is composed of Josephson junction transmission lines, along which localized magnetic flux can propagate. By choosing bias current properly, the duplication of magnetic flux and a variety of logical functions can be obtained without changing the circuit topology. Computer simulation results are presented on AND and OR operations with two and three inputs for the same circuit topology, confirming that these circuits can be used as logic circuits. The simulations demonstrate the high-speed operation and low power consumption of this circuit.>
We describe a one-bit full adder circuit constructed from direct-coupled Josephson logic elements. The basic gate, which can perform various logic functions, consists of two Josephson junctions and two resistors connected in a loop. Switching the junctions into the finite-voltage state diverts the bias current into a parallel output line, which is directly coupled through the junctions of successive logic elements. The adder is constructed with a 100 μm basic linewidth and 25 μm square tin tunnel junctions. It operates under all input data conditions with an add time of about 1 nS and a power dissipation of 1 μW per gate.