We report progress toward the development of a quantum silicon-on-insulator (QSOI(R)) technology compatible with 300mm CMOS fabrication and adapted from the 28nm Fully-Depleted SOI (28nm FD-SOI) platform for scalable quantum computing. We compare quantum devices fabricated with standard 28nm FD-SOI and QSOI(R) technologies, and show striking improvements of room temperature electrostatic properties of the individual device. Moreover, the QSOI(R) technology has significantly reduced the device variability and the dispersion of device properties at the wafer level. Transistor metrics are reproduced by TCAD simulations showing that the electrostatics of the devices behave as expected for QSOI(R) technology. Wafer-scale measurements at sub-2K show reproducible quantum dots down to the few-electron regime with 69\% yield for successful charge detection of the first electron and a dispersion of the first electron position of $\mathrm{\pm 35 mV}$ over 377 quantum dots. These results establish QSOI(R) as a promising platform for CMOS-compatible quantum device co-integration.
We report progress toward the development of a quantum silicon-on-insulator (QSOI(R)) technology compatible with 300mm CMOS fabrication and adapted from the 28nm Fully-Depleted SOI (28nm FD-SOI) platform for scalable quantum computing. We compare quantum devices fabricated with standard 28nm FD-SOI and QSOI(R) technologies, and show striking improvements of room temperature electrostatic properties of the individual device. Moreover, the QSOI(R) technology has significantly reduced the device variability and the dispersion of device properties at the wafer level. Transistor metrics are reproduced by TCAD simulations showing that the electrostatics of the devices behave as expected for QSOI(R) technology. Wafer-scale measurements at sub-2K show reproducible quantum dots down to the few-electron regime with 69% yield for successful charge detection of the first electron and a dispersion of the first electron position of ±35mV over 377 quantum dots. These results establish QSOI(R) as a promising platform for CMOS-compatible quantum device co-integration.
Quantum computers require interfaces with classical electronics for efficient qubit control, measurement and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offer potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-transistor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large scale circuits. Here we demonstrate the integration of a single-electron charge storage CMOS quantum dot with a CMOS transistor for control of the readout via gate-based dispersive sensing using a lumped element LC resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully-depleted silicon-on-insulator technology. We obtain a charge sensitivity of δq=165μeHz−1/2 when the quantum dot readout is enabled by the control FET. Additionally, we observe a single-electron retention time of the order of a second when storing a single-electron charge on the quantum dot at milli-Kelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive qubit readout in CMOS technology opening the path for the development of an all-silicon quantum-classical processor.
Building quantum computers requires not only a large number of qubits with high fidelity and low variability, but also a large amount of analog and digital components to drive the qubits. Larger arrays of solid-state qubits with high fidelity and low variability require improvements in fabrication processes and array layout design co-optimized with the underlying hardware technology. Here we outline progress on 300mm fabrication of qubit devices and on classical CMOS components to enable the quantum system. We describe work on superconducting qubits and spin qubits in Si, both types of devices fabricated on 300mm experimental platforms and discuss challenges related to variability. Massive electrical characterization is key over wide temperature range is key to enabling system upscaling for QC.
The proliferation of quantum computing technologies has fueled the race to build a practical quantum computer. The spectrum of the innovation is wide and encompasses many aspects of this technology, such as the qubit, control and detection mechanism, cryogenic electronics, and system integration. A few of those emerging technologies are poised for successful monolithic integration of cryogenic electronics with the quantum structure where the qubits reside. In this work, we present a fully integrated Quantum Processor Unit in which the quantum core is co-located with control and detection circuits on the same die in a commercial 22-nm FD-SOI process from GlobalFoundries. The system described in this work comprises a two dimensional (2D) 240 qubits array integrated with 8 detectors and 32 injectors operating at 3K and inside a two-stage Gifford-McMahon cryo-cooler. The power consumption of each detector and injector is 1mW and 0.27mW, respectively. The control sequence is programmed into an on-chip pattern generator that acts as a command and control block for all hardware in the Quantum Processor Unit. Using the aforementioned apparatus, we performed a quantum resonant tunneling experiment on two qubits inside the 2D qubit array. With supporting lab measurements, we demonstrate the feasibility of the proposed architecture in scaling-up the existing quantum core to thousands of qubits.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
Quantum computing is predicted to provide unprecedented enhancements in computational power. A quantum computer requires implementation of a well-defined and controlled quantum system of many interconnected qubits, each defined using fragile quantum states. The interest in a spin-based quantum computer in silicon stems from demonstrations of very long spin-coherence times, high-fidelity single spin control and compatibility with industrial mass-fabrication. Industrial scale fabrication of the silicon platform offers a clear route towards a large-scale quantum computer, however, some of the processes and techniques employed in qubit demonstrators are incompatible with a dense and foundry-fabricated architecture. In particular, spin-readout utilises external sensors that require nearly the same footprint as qubit devices. In this thesis, improved readout techniques for silicon quantum devices are presented and routes towards implementation of a scalable and high-sensitivity readout architecture are investigated. Firstly, readout sensitivity of compact gate-based sensors is improved using a high-quality factor resonator and Josephson parametric amplifier that are fabricated separately from quantum dots. Secondly, an integrated transistor-based control circuit is presented using which sequential readout of two quantum dot devices using the same gate-based sensor is achieved. Finally, a large-scale readout architecture based on random-access and frequency multiplexing is introduced. The impact of readout circuit footprint on readout sensitivity is determined, showing routes towards integration of conventional circuits with quantum devices in a dense architecture, and a fault-tolerant architecture based on mediated exchange is introduced, capable of relaxing the limitations on available control circuit footprint per qubit. Demonstrations are based on foundry-fabricated transistors and few-electron quantum dots, showing that industry fabrication is a viable route towards quantum computation at a scale large enough to begin addressing the most challenging computational problems.
With the progress made in advanced semiconductor manufacturing and in control and readout techniques, semiconductor based quantum computing has made significant progress in the past decade in both fidelities and coherence times. In view of scalability, an elementary computational unit that can retain key computational functionalities must be defined so that an array of such units can process information without excessive overhead. For quantum computation to proceed, not only should each qubit be able to perform operations in all dimensions about the Bloch sphere, but the detection of quantum states, either spin or charge, should also be fast, robust, and efficient. As the number of ancilla qubits needed for error correction scales with the number of computational qubits, there is a need for highly scalable, reproducible designs with a density sufficient to allow error correction. Finally, a cost-effective solution that maintains high compatibility with industry standards is needed to ensure industrialisation of such a unit. A compact arrangement eases scalability and allows a higher qubit density, while the versatility of such an architecture allows the circumvention of potentially defective or otherwise unusable portions of large-scale structures. This would allow minimising the footprint typically dedicated to error correction. This thesis proposes such an elementary unit in the form of a quadruple quantum-dot fabricated by a standard silicon-based Complementary metal- oxide-semiconductor (CMOS) process. Firstly, we show the flexibility of this device by reconfiguring the structure as a single-electron box (SEB) detector and as various double-quantum-dot (DQD) detector configurations. In all cases, we demonstrate a high fidelity fast readout exceeding 99.8% in 10µs. Finally, we discuss the ability for the DQD detector to exceed the performance of the SEB detector in an isolated quantum-dot array by thermalising with the lower temperature of T ≈42 ±2 mK as opposed to the electron temperature Te ≈139 ±4 mK.