Quantum compilation reconciles a program's idealized interaction topology with hardware locality constraints, yet evaluations at scale lack calibrated references for realization overhead. We present QROB, a scalable reverse-construction methodology that generates compilation instances backward from directly realizable configurations, retaining the inverse paths as feasible, compiler-independent references. QROB provides a common evaluation substrate for NISQ SWAP routing and fault-tolerant lattice-surgery scheduling, while extending its reference-preserving principle to capacity-constrained quantum memory-access scheduling.
Across systems ranging from 9 to 156 qubits, evaluations highlight QROB's utility as both a diagnostic benchmark and a data source. First, for compiler characterization, QROB reveals substantial realization gaps in existing tools, with NISQ compilers incurring up to 24.1x the reference SWAP cost and fault-tolerant compilers requiring up to 7.0x the reference makespan. Second, as a supervision source for data-driven compilation, a router trained on QROB references outperforms Qiskit SABRE on 84.8% of real-world application circuits. Finally, on real hardware, QROB reference realizations achieve a median mirror-circuit survival rate 1.65x that of full Qiskit O3 compilations across three 156-qubit IBM Heron-r2 processors, demonstrating that closing algorithmic compilation gaps translates directly into physical fidelity gains.
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Accepted to the 59th IEEE/ACM International Symposium on Microarchitecture (MICRO 2026)
Quantum compilation reconciles a program's idealized interaction topology with hardware locality constraints, yet evaluations at scale lack calibrated references for realization overhead. We present QROB, a scalable reverse-construction methodology that generates compilation instances backward from directly realizable configurations, retaining the inverse paths as feasible, compiler-independent references. QROB provides a common evaluation substrate for NISQ SWAP routing and fault-tolerant lattice-surgery scheduling, while extending its reference-preserving principle to capacity-constrained quantum memory-access scheduling.
Across systems ranging from 9 to 156 qubits, evaluations highlight QROB's utility as both a diagnostic benchmark and a data source. First, for compiler characterization, QROB reveals substantial realization gaps in existing tools, with NISQ compilers incurring up to 24.1x the reference SWAP cost and fault-tolerant compilers requiring up to 7.0x the reference makespan. Second, as a supervision source for data-driven compilation, a router trained on QROB references outperforms Qiskit SABRE on 84.8% of real-world application circuits. Finally, on real hardware, QROB reference realizations achieve a median mirror-circuit survival rate 1.65x that of full Qiskit O3 compilations across three 156-qubit IBM Heron-r2 processors, demonstrating that closing algorithmic compilation gaps translates directly into physical fidelity gains.
Quantum programming languages and their compilers form the critical software layer between abstract quantum algorithm specifications and physical hardware execution -- yet compiler quality varies enormously across the quantum software ecosystem, with suboptimal compilation directly increasing circuit depth, gate count, and consequently error rates on NISQ hardware. This paper proposes the Quantum Compiler Design and Evaluation (QCDE) framework, a systematic methodology for quantum compiler optimisation across four compilation stages: gate synthesis (decomposing abstract gates to hardware-native gate sets), routing (mapping virtual qubits to physical qubits under connectivity constraints), scheduling (ordering gates to minimise decoherence), and cross-layer optimisation (combining all stages with error mitigation awareness). QCDE evaluates six quantum compilers (Qiskit transpiler L1-L3, TKET, BQSKit, Cirq, Quilc, and a novel QCDE-Opt compiler) on 48 benchmark circuits from the QOAS, HQCAD, and QNNDE algorithm ecosystems. QCDE-Opt achieves 18.4% lower CX gate count vs. Qiskit L3 (best existing compiler) through a novel error-aware peephole optimisation pass. BQSKit provides the best synthesis quality at 28.4% CX reduction but 12.4x compilation overhead. TKET achieves the best balance of quality and speed (8.4% CX reduction, 1.8x overhead). QCDE provides a compiler selection guide and the QCDE-Opt compiler as an open-source contribution.
Current superconducting quantum devices impose strict connectivity constraints on quantum circuit execution, necessitating circuit transformation before executing quantum circuits on physical hardware. Numerous quantum circuit transformation (QCT) algorithms have been proposed. To enable faithful evaluation of state-of-the-art QCT algorithms, this paper introduces (Qubit mapping Benchmark with Known Near-Optimality), a novel benchmark construction method for QCT. QKNOB circuits have built-in transformations with near-optimal (close to the theoretical optimum) SWAP count and depth overhead. QKNOB provides general and unbiased evaluation of QCT algorithms. Using QKNOB, we demonstrate that SABRE, the default Qiskit compiler, consistently achieves the best performance on the 53-qubit IBM Q Rochester and Google Sycamore devices for both SWAP count and depth objectives. Our results also reveal significant performance gaps relative to the near-optimal transformation costs of QKNOB. Our construction algorithm and benchmarks are open-source.
Achieving practical quantum advantage on fault-tolerant quantum computers (FTQC) is fundamentally constrained by the substantial spatial and temporal overheads required to map logical operations onto physical hardware. Existing compilation approaches typically adopt coarse-grained, slice-based abstractions that overlook fine-grained microarchitectural effects, such as routing contention, leading to inefficient resource utilization and limited alignment between algorithm structure and hardware capabilities.
We introduce Qomet, a microarchitecture-aware compiler that tightly couples algorithmic properties with lattice surgery (LS) execution. By exploiting C-Phase gate commutativity, Qomet translates sequential operations into simultaneous multi-target interactions, natively leveraging LS to eliminate false dependencies and expose instruction-level parallelism. To support this, Qomet employs an adaptive, event-driven scheduler that captures precise spatial and routing constraints to overlap instructions temporally. By minimizing grid idling and routing contention, Qomet achieves a geometric-mean execution speedup of 4.29× and a maximum speedup of 59.7× across realistic workloads.
Realizing a conceptual quantum algorithm on an actual physical device necessitates the algorithm's quantum circuit description to undergo certain transformations in order to adhere to all constraints imposed by the hardware. In this regard, the individual high-level circuit components are first synthesized to the supported low-level gate-set of the quantum computer, before being mapped to the target's architecture-utilizing several optimizations in order to improve the compilation result. Specialized tools for this complex task exist, e.g., IBM's Qiskit, Google's Cirq, Microsoft's QDK, or Rigetti's Forest. However, to date, the circuits resulting from these tools are hardly verified, which is mainly due to the immense complexity of checking if two quantum circuits indeed realize the same functionality. In this paper, we propose an efficient scheme for quantum circuit equivalence checking-specialized for verifying results of the IBM Qiskit quantum circuit compilation flow. To this end, we combine characteristics unique to quantum computing, e.g., its inherent reversibility, and certain knowledge about the compilation flow into a dedicated equivalence checking strategy. Experimental evaluations confirm that the proposed scheme allows to verify even large circuit instances with tens of thousands of operations within seconds or even less, whereas state-of-the-art techniques frequently time-out or require substantially more runtime. A corresponding open source implementation of the proposed method is publicly available at https://github.com/iic-jku/qcec.
Realizing fault-tolerant quantum computing requires mapping logical programs to heterogeneous quantum error correction (QEC) codes and diverse fault-tolerant execution models, scheduling physical resources, and coupling to real-time classical control and feedback. Specialized tools exist for each step but rely on manual composition and translation that discard assumptions and provenance, separating resource estimates from the compiler artifacts they describe, and making it difficult to validate correctness, compare architectures, or attribute costs to specific design choices. We present CUDA-Q Logical, an extensible compiler infrastructure for retargetable fault-tolerant compilation, analysis, and execution. Interoperable with CUDA-Q and other mainstream front-ends, CUDA-Q Logical progressively lowers target-independent logical programs through a constrained logical virtual machine, QEC microcode, physical gate schedules, and real-time control plans, with each layer preserving semantics and provenance, while verifying composition and resource constraints. By deriving every resource estimate directly from compiler artifacts, the framework unifies compilation and resource analysis, enabling successively refined estimates and principled cross-architecture comparison while permitting QEC codes, execution models, decoders, and hardware architectures to be introduced as modular extensions. Across workloads ranging from application-architecture studies to qLDPC surgery and detector-error-model composition, we show that schedule-derived estimates reconcile with established independent models. Crucially, this compiler-visible structure exposes cost drivers hidden by aggregate analytical formulas, carries QEC artifacts intact into simulation, and demonstrates a complete compilation pipeline for fault-tolerant quantum computing.
Abstract Calibration summaries are used both to select physical qubits and to parameterize noisy emulators, creating a risk that agreement within a calibration-derived model is mistaken for validation on hardware. We test whether calibration-aware compiler rankings transfer to hardware using weighted-MaxCut instances implemented with the quantum approximate optimization algorithm. The evidence comprises four stages: 3240 historical calibration-derived simulations; a complete 54-pair hardware grid on three IBM Heron r2 processors; exact-circuit repeats 9.3–12.1 d later; and a contemporaneous five-arm refresh experiment. Full-calibration selection improves the median hardware approximation ratio by 0.74 percentage points (pp), with 29 resolved gains and 11 resolved losses. This is a mean-objective effect: its translation to exact-solution probability is instance- and size-dependent, and we do not extrapolate it beyond the tested n ⩽ 10 regime. A Qiskit Aer model constructed from the calibration state available before execution reproduced the direction of the measured full-calibration-versus-topology advantage in 35/54 comparisons, but systematically overestimated its size: the simulated advantage exceeded the subsequently measured hardware advantage by a median 1.35 pp. Regressing the measured hardware advantage on the simulated advantage gave a slope of 0.28 (workload-depth case-cluster 95% interval 0.06–0.52), rather than the unit slope of a calibrated predictor. The emulator identified the exact best of six backend-compiler configurations in only 5/18 cases (95% Wilson interval [0.125, 0.509]). By contrast, identical circuits preserved the compiler-effect sign in 16/18 later repeats ( r = 0.92 ). Refreshing the full-calibration mapping yielded a median +0.72 pp gain, whereas the calibration-score difference agreed in sign with the measured refresh benefit in only 9/18 cases. Calibration data are therefore useful for candidate discovery and timely refresh, but their scalar scores are not calibrated predictors of hardware performance or configuration ranking.