Quantum programming languages and their compilers form the critical software layer between abstract quantum algorithm specifications and physical hardware execution -- yet compiler quality varies enormously across the quantum software ecosystem, with suboptimal compilation directly increasing circuit depth, gate count, and consequently error rates on NISQ hardware. This paper proposes the Quantum Compiler Design and Evaluation (QCDE) framework, a systematic methodology for quantum compiler optimisation across four compilation stages: gate synthesis (decomposing abstract gates to hardware-native gate sets), routing (mapping virtual qubits to physical qubits under connectivity constraints), scheduling (ordering gates to minimise decoherence), and cross-layer optimisation (combining all stages with error mitigation awareness). QCDE evaluates six quantum compilers (Qiskit transpiler L1-L3, TKET, BQSKit, Cirq, Quilc, and a novel QCDE-Opt compiler) on 48 benchmark circuits from the QOAS, HQCAD, and QNNDE algorithm ecosystems. QCDE-Opt achieves 18.4% lower CX gate count vs. Qiskit L3 (best existing compiler) through a novel error-aware peephole optimisation pass. BQSKit provides the best synthesis quality at 28.4% CX reduction but 12.4x compilation overhead. TKET achieves the best balance of quality and speed (8.4% CX reduction, 1.8x overhead). QCDE provides a compiler selection guide and the QCDE-Opt compiler as an open-source contribution.
Quantum programming languages and their compilers form the critical software layer between abstract quantum algorithm specifications and physical hardware execution -- yet compiler quality varies enormously across the quantum software ecosystem, with suboptimal compilation directly increasing circuit depth, gate count, and consequently error rates on NISQ hardware. This paper proposes the Quantum Compiler Design and Evaluation (QCDE) framework, a systematic methodology for quantum compiler optimisation across four compilation stages: gate synthesis (decomposing abstract gates to hardware-native gate sets), routing (mapping virtual qubits to physical qubits under connectivity constraints), scheduling (ordering gates to minimise decoherence), and cross-layer optimisation (combining all stages with error mitigation awareness). QCDE evaluates six quantum compilers (Qiskit transpiler L1-L3, TKET, BQSKit, Cirq, Quilc, and a novel QCDE-Opt compiler) on 48 benchmark circuits from the QOAS, HQCAD, and QNNDE algorithm ecosystems. QCDE-Opt achieves 18.4% lower CX gate count vs. Qiskit L3 (best existing compiler) through a novel error-aware peephole optimisation pass. BQSKit provides the best synthesis quality at 28.4% CX reduction but 12.4x compilation overhead. TKET achieves the best balance of quality and speed (8.4% CX reduction, 1.8x overhead). QCDE provides a compiler selection guide and the QCDE-Opt compiler as an open-source contribution.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
Quantum computing, leveraging the principles of superposition and entanglement, holds the potential to revolutionize computational problem-solving across a wide array of fields, from cryptography to complex system simulations. However, unlocking the full power of quantum computing requires the development of advanced quantum compilation techniques that can efficiently map high-level algorithms onto physical quantum hardware. This paper delves into state-of-the-art optimization strategies within quantum compilers, with a particular focus on methods such as Relaxed Peephole Optimization (RPO), gate reordering techniques for the Quantum Approximate Optimization Algorithm (QAOA), and reinforcement learning (RL)-driven frameworks. It also explores innovative approaches like distributed quantum compilation, parity quantum optimization, and the Paulihedral framework, all designed to minimize gate counts, reduce circuit depth, and optimize overall resource utilization. A key contribution of this work is the introduction of error mitigation techniques that enhance the fidelity and scalability of quantum circuits, particularly on noisy intermediate-scale quantum (NISQ) devices. Through comprehensive empirical evaluations across a variety of quantum algorithms, the paper demonstrates significant improvements in critical performance metrics such as circuit depth, gate count, and execution efficiency, providing a promising direction for optimizing quantum circuit design tailored to diverse quantum hardware platforms.
Efficient compilation of quantum algorithms is vital in the era of Noisy Intermediate-Scale Quantum (NISQ) devices. While multiple open-source quantum compilation and circuit optimization frameworks are available, e.g. IBM Qiskit, CQC Tket, Google Cirq, Rigetti Quilc, PyZX, their relative performance is not always clear to a quantum programmer. The growth of complexity and diversity of quantum circuit compilation algorithms creates a demand for a dedicated tool for cross-benchmarking and profiling of inner workflow of the quantum compilation stack. We present an open-source software package, Arline Benchmarks, that is designed to perform automated benchmarking of quantum compilers with the focus on NISQ applications. The name "Arline" was given in honour of Arline Greenbaum Feynman, the first wife of Richard Feynman, the pioneer of quantum computing. We compared several quantum compilation frameworks based on a set of important metrics such as post-optimization gate counts, circuit depth, hardware-dependent circuit cost function, compiler run time etc. with a detailed analysis of metrics for each compilation stage. We performed a variety of compiler tests for random circuits and structured quantum algorithms (VQE, Trotter decomposition, Grover search, Option Pricing via Amplitude Estimation) for several popular quantum hardware architectures. Leveraging cross-platform functionality of Arline, we propose a concept of composite compilation pipeline that combines compiler-specific circuit optimization subroutines in a single compilation stack and finds an optimized sequence of compilation passes. By providing detailed insights into the compilation flow of quantum compilers, Arline Benchmarks offers a valuable toolkit for quantum computing researchers and software developers to gain additional insights into compilers' characteristics.
Quantum circuit compilation is a multi-stage process that translates a high-level quantum circuit representation into a sequence of quantum gates that can be directly executed by a quantum machine. One of the core steps in quantum compilation is mapping, a procedure that transforms a quantum circuit into a semantically equivalent circuit while inserting additional gates to comply with the architectural constraints of the underlying quantum hardware. Current mapping techniques exhibit significant performance degradation—in terms of circuit depth and gate count—when applied to large-scale circuits containing hundreds of thousands of gates or more. In this work, we propose a novel methodology to enhance quantum compiler capabilities by adapting general principles from classical Electronic Design Automation. We model the quantum hardware as being composed of standard cells, onto which portions of the circuit are mapped using a floorplanning-based technique. This contrasts with current state-of-the-art solutions, which perform mapping at the gate level without considering any form of hierarchical abstraction. We use the ChaCha20 stream cipher as a running example to validate and explain our strategy. We evaluate our methodology using two well-known, industrial-grade quantum compilers: IBM Qiskit and Quantinuum TKET. Compared to these compilers, our approach achieves an average circuit depth reduction of 59.78% and 68.85%, respectively, and a gate count reduction of 4.07 % and 6.20 %, respectively. These results are obtained across a large set of randomly generated quantum circuit descriptions in the range of millions of gates, with varying input and output connectivity for each block in the circuit.
Quantum circuit compilation is a critical step in realizing quantum algorithms on real quantum hardware. Traditional compilation methods often employ static optimization strategies, neglecting the unique constraints and characteristics of the target quantum device. This paper introduces a novel adaptive quantum circuit compilation framework designed to dynamically adjust circuit designs based on hardware-specific information, aiming to minimize gate count and, consequently, error rates. The core of the framework lies in integrating a hardware simulator directly within the compilation process. This allows the compiler to evaluate the performance of various circuit designs—considering factors like qubit connectivity, gate fidelity, and decoherence models—before committing to a final layout. The proposed approach represents a shift from static to adaptive optimization, providing a more nuanced and effective strategy for translating quantum algorithms into executable code on diverse quantum hardware platforms. This research demonstrates a significant potential improvement in quantum circuit efficiency and fidelity, addressing a key bottleneck in the advancement of quantum computing.