Dynamic quantum circuits (DQCs) provide a hardware-efficient route to quantum computing by reducing physical-qubit overhead and compressing circuit topology through mid-circuit measurements, qubit reset and reuse, and classical feed-forward control. Here, we demonstrate the advantages of DQCs on a single hybrid superconducting qubit-cavity processor by implementing a hierarchy of algorithms with increasing complexity. This hybrid architecture consists of a high-dimensional cavity qudit serving as the computational register and a dispersively coupled superconducting transmon ancilla that is repeatedly measured, reset, and reused to enable dynamic control. Using this device, we implement a 10-bit Bernstein-Vazirani algorithm with an average success probability of 82%, surpassing state-of-the-art dynamic and static implementations in both scale and performance; an 8-bit quantum phase-estimation protocol with estimation errors below 10-3; and the first dynamic-circuit implementation of Shor's algorithm on a superconducting platform, factoring 15 over all coprime bases with squared statistical overlap values above 99.8%. These results provide concrete benchmarks for future DQC implementations and highlight the versatile advantages of DQCs with the hybrid qubit-qudit architecture, establishing it as a promising route toward scalable, programmable quantum computation.
Dynamic quantum circuits (DQCs) provide a hardware-efficient route to quantum computing by reducing physical-qubit overhead and compressing circuit topology through mid-circuit measurements, qubit reset and reuse, and classical feed-forward control. Here, we demonstrate the advantages of DQCs on a single hybrid superconducting qubit-cavity processor by implementing a hierarchy of algorithms with increasing complexity. This hybrid architecture consists of a high-dimensional cavity qudit serving as the computational register and a dispersively coupled superconducting transmon ancilla that is repeatedly measured, reset, and reused to enable dynamic control. Using this device, we implement a 10-bit Bernstein-Vazirani algorithm with an average success probability of 82%, surpassing state-of-the-art dynamic and static implementations in both scale and performance; an 8-bit quantum phase-estimation protocol with estimation errors below 10-3; and the first dynamic-circuit implementation of Shor's algorithm on a superconducting platform, factoring 15 over all coprime bases with squared statistical overlap values above 99.8%. These results provide concrete benchmarks for future DQC implementations and highlight the versatile advantages of DQCs with the hybrid qubit-qudit architecture, establishing it as a promising route toward scalable, programmable quantum computation.
The execution of large-scale quantum algorithms is currently constrained by the limited number of available qubits, qubit connectivity restrictions, and the inherent noise in quantum processors. To address these limitations, a design methodology known as Dynamic Quantum Circuits (DQC) has emerged. DQC leverages non-unitary operations-such as active reset, midcircuit measurement, and classically controlled gate operationsto reduce qubit requirements during circuit design. Recently, DQC-based implementations have been explored for various algorithms, including Shor’s Prime Factorization, Quantum Phase Estimation (QPE), and Bernstein-Vazirani (BV), as well as for key operations like state preparation, Toffoli networks, and nonlocal gates. While DQC offers a significant reduction in qubit usage, it introduces a trade-off in the form of increased circuit depth. Therefore, assessing the reliability of such circuits becomes crucial in the context of current quantum hardware architectures. In this paper, we analyze the reliability of DQC-based quantum circuit realizations as a function of qubit count and circuit depth. We present empirical results for two algorithms and evaluate how architectural parameters impact their reliability.
Recent advances in fault tolerant quantum systems allow to perform non-unitary operations like mid-circuit measurement, active reset and classically controlled gate operations in addition to the existing unitary gate operations. Real quantum devices that support these non-unitary operations enable us to execute a new class of quantum circuits, known as Dynamic Quantum Circuits (DQC). This helps to enhance the scalability, thereby allowing execution of quantum circuits comprising of many qubits by using at least two qubits. Recently DQC realizations of multi-qubit Quantum Phase Estimation (QPE) and Bernstein-Vazirani (BV) algorithms have been demonstrated in two separate experiments. However the dynamic transformation of complex quantum circuits consisting of Toffoli gate operations have not been explored yet. This motivates us to: (a) explore the dynamic realization of Toffoli gates by extending the design space of DQC for Toffoli networks, and (b) propose a general dynamic transformation algorithm for the first time to the best of our knowledge. More precisely, we introduce two dynamic transformation schemes (dynamic-1 and dynamic-2) for Toffoli gates, that differ with respect to the required number of classically controlled gate operations. For evaluation, we consider the Deutsch-Jozsa (DJ) algorithm composed of one or more Toffoli gates. Experimental results demonstrate that dynamic DJ circuits based on dynamic-2 Toffoli realization scheme provides better computational accuracy over the dynamic-1 scheme. Further, the proposed dynamic transformation scheme is generic and can also be applied to non-Toffoli quantum circuits, e.g. BV algorithm.
Scaling up to a large number of qubits with high-precision control is essential in the demonstrations of quantum computational advantage to exponentially outpace the classical hardware and algorithmic improvements. Here, we develop a two-dimensional programmable superconducting quantum processor, Zuchongzhi, which is composed of 66 functional qubits in a tunable coupling architecture. To characterize the performance of the whole system, we perform random quantum circuits sampling for benchmarking, up to a system size of 56 qubits and 20 cycles. The computational cost of the classical simulation of this task is estimated to be 2-3 orders of magnitude higher than the previous work on 53-qubit Sycamore processor [Nature 574, 505 (2019)NATUAS0028-083610.1038/s41586-019-1666-5. We estimate that the sampling task finished by Zuchongzhi in about 1.2 h will take the most powerful supercomputer at least 8 yr. Our work establishes an unambiguous quantum computational advantage that is infeasible for classical computation in a reasonable amount of time. The high-precision and programmable quantum computing platform opens a new door to explore novel many-body phenomena and implement complex quantum algorithms.
In dynamic quantum circuits, classical information from midcircuit measurements is fed forward during circuit execution. This emerging capability of quantum computers confers numerous advantages that can enable more efficient and powerful protocols by drastically reducing the resource requirements for certain core algorithmic primitives. In particular, in the case of the n-qubit quantum Fourier transform followed immediately by measurement, the scaling of resource requirements is reduced from O(n^{2}) two-qubit gates in an all-to-all connectivity in the standard unitary formulation to O(n) midcircuit measurements in its dynamic counterpart without any connectivity constraints. Here, we demonstrate the advantage of dynamic quantum circuits for the quantum Fourier transform on IBM's superconducting quantum hardware with certified process fidelities of >50% on up to 16 qubits and >1% on up to 37 qubits, exceeding previous reports across all quantum computing platforms. These results are enabled by our contribution of an efficient method for certifying the process fidelity, as well as of a dynamical decoupling protocol for error suppression during midcircuit measurements and feed forward within a dynamic quantum circuit that we call "feed-forward-compensated dynamical decoupling." Our results demonstrate the advantages of leveraging dynamic circuits in optimizing the compilation of quantum algorithms.
In this work we have presented design for scalability (DFS) for compiling dynamic quantum circuits in order to execute them on centralized monolithic or distributed environment. Dynamic quantum circuits allow the usage of mid-circuit measurement, active reset and classically controlled quantum operations for circuit designs. Since, quantum algorithms solving practical complex problems involve thousands of qubits that a targeted computing environments may not provide, it has become crucial to seek for schemes that enable dynamic circuit realization of such algorithms using less number of qubits to make them executable on the selected hardware platforms. To this end we have considered two different quantum circuits representing Bernstein–Vazirani Algorithm (BVA) and Variational Quantum Circuit (VQC) for deep Q network, and two computing environments, monolithic and distributed for framing our design solutions. For the monolithic environment we have shown that using only two qubits dynamic version of both these BVA and VQC are achievable. In the distributed environment with quantum communication channel being in place, the corresponding distributed design are also obtained by employing one or more such communication channels. We have also shown that even with structural similarities between the worst-case BVA (featuring a secret string of all 1s) and the VQC, the design alternatives might differ depending on the noise level of the chosen distributed hardware platform.
Quantum error correction using erasure qubits offers higher fault-tolerant thresholds and improved scaling by converting dominant physical errors into detectable erasures. In superconducting circuits, erasure qubits can be constructed using the dual-rail approach, which, however, requires additional qubit-count overhead and tailored coupling elements. Here, we demonstrate a hardware-efficient scheme that operates transmon qutrits as erasure qubits, which is compatible with standard superconducting circuit-QED hardware. The logical states ∣0L⟩ and ∣1L⟩ are represented by the ground and second excited states, while the dominant relaxation errors can be detected via an ancilla qubit using a microwave-activated two-qutrit SWAP gate. We demonstrate a logical qubit T1 lifetime exceeding 500μs, post-selected with repeated mid-circuit erasure detection, which is ten times longer than the T1 time of the transmon physical qubit. Coherence times beyond 300μs are achieved using dynamical decoupling. Single-qubit gate operations reach average Clifford gate infidelity on the order of 10−4. We further demonstrate dual-purposing an ancilla qubit for both erasure detection and parity checking, showing heralded generation of Bell states between erasure qubits. These results suggest that mainstream architectures of transmon qubit arrays may already be capable of implementing erasure-based QEC strategies for hardware-efficient fault-tolerant quantum computing.