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arXiv:2607.23529

Single-Aperture Dual-Color Ion Addressing with a DUV-Compatible Bilayer Grating

Gyanendra Yadav

quant-phphysics.opticsSubmitted Jul 26, 2026• Announced Jul 28, 2026• 0 citations
v1 · Jul 26, 2026v2 · Sep 20, 2026
arXivHTMLPDF

Abstract

Multi-wavelength optical control is a scaling bottleneck for trapped-ion hardware: separate surface emitters consume trap area, interrupt the electrode plane, and expose charge-sensitive dielectric near the ions. Here, a vertically stacked silicon-nitride bilayer routes the $^{40}\text{Ca}^+$ qubit and repump fields-729.4 and 854.2 nm-through one electrode aperture and focuses them $70~μ\text{m}$ above the chip. Three-dimensional FDTDX predicts $0.10~μ\text{m}$ color separation and near-diffraction-limited spots along the ion-chain axis. Multi-level depth-allocation apodization enables this architecture by encoding the coupling envelope in discrete etch levels rather than sub-resolution linewidths. Every feature satisfies a strict $\ge 125\text{ nm}$ deep-UV rule using two etch depths per film. Full-3D Ansys Lumerical simulations independently corroborate directionality, spot size, and repump efficiency. At a common 50 nm reporting grid, the DUV-compatible device matches a 63 nm electron-beam design on the qubit channel (focusing efficiency 0.286 vs 0.288; crosstalk -24.0 vs -24.3 dB). Vertical integration therefore converts wavelength scaling from a lateral-footprint penalty into a layer-allocation problem, providing a pathway toward compact multi-color photonic interfaces for trapped ions and other chip-addressed quantum emitters.

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Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. 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The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. 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In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. 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•Jun 26, 2026•0 citations
Multi-wavelength optical control is a scaling bottleneck for trapped-ion hardware: separate surface emitters consume trap area, interrupt the electrode plane, and expose charge-sensitive dielectric near the ions. Here, a vertically stacked silicon-nitride bilayer routes the 40Ca+^{40}\text{Ca}^+40Ca+ qubit and repump fields-729.4 and 854.2 nm-through one electrode aperture and focuses them 70 μm70~μ\text{m}70 μm above the chip. Three-dimensional FDTDX predicts 0.10 μm0.10~μ\text{m}0.10 μm color separation and near-diffraction-limited spots along the ion-chain axis. Multi-level depth-allocation apodization enables this architecture by encoding the coupling envelope in discrete etch levels rather than sub-resolution linewidths. Every feature satisfies a strict ≥125 nm\ge 125\text{ nm}≥125 nm deep-UV rule using two etch depths per film. Full-3D Ansys Lumerical simulations independently corroborate directionality, spot size, and repump efficiency. At a common 50 nm reporting grid, the DUV-compatible device matches a 63 nm electron-beam design on the qubit channel (focusing efficiency 0.286 vs 0.288; crosstalk -24.0 vs -24.3 dB). Vertical integration therefore converts wavelength scaling from a lateral-footprint penalty into a layer-allocation problem, providing a pathway toward compact multi-color photonic interfaces for trapped ions and other chip-addressed quantum emitters.
Trapped ions provide a high-fidelity platform for quantum information processing, yet delivery of multiple, distinct wavelengths across large networks of interaction zones remains a bottleneck. Conventional free-space light delivery lacks scalability, while on-chip grating couplers suffer from narrow operational bandwidth that increases circuit footprint and optical interfacing complexity. Here we show a broadband photonic integrated circuit capable of addressing individual ions. The circuit combines a planar waveguide lens with a micromirror fabricated using two-photon polymerization at wafer scale. This implementation can address three individual ions from λλλ = 405 - 880 nm with -27 dB average intensity crosstalk at 5 μm5\,μ\mathrm{m}5μm pitch. We trap 40Ca+^{40}\mathrm{Ca}^{+}40Ca+ and 138Ba+^{138}\mathrm{Ba}^{+}138Ba+ ions above such devices, characterize optical crosstalk with barium ions, and demonstrate individual repumping of calcium ions. This monolithic photonic architecture brings broadband addressing in an on-chip modality to trapped-ion technology. More generally, integrating additive manufacturing into quantum devices is poised to unlock expanded design space for implementing novel quantum architectures.
Trapped-ion quantum computing requires precise optical control for individual qubit manipulation. However, conventional free-space optics face challenges in alignment stability and scalability as the number of qubits increases. Integrated photonics offers a promising alternative, providing miniaturized optical systems on a chip. Here, we propose a design for a multimode photonic circuit integrated with a surface-electrode ion trap capable of targeted and reconfigurable light delivery. Three closely positioned ions can be addressed using a focusing grating coupler that emits multimode light through electrode openings to ions trapped 80 μμμm above the chip. Simulations show that the couplers achieve diffraction-limited spot with a 4.3 μμμm beam waist along the trap axis and 2.2 μμμm perpendicular to the trap axis. Controlled interference of the TE10_{\text{10}}10​ and TE20_{\text{20}}20​ modes results in crosstalk of -20 dB to -30 dB at ion separations of 5-8 μμμm when addressing ions individually, and down to -60 dB when two of the three ions are addressed simultaneously. Additionally, the higher-order TE modes can offer a novel mechanism for driving spin-motion coupling transitions, potentially enabling alternative approaches to quantum gates and simulations. The proposed integrated platform offers a viable path for constructing large-scale trapped-ion systems, leveraging the benefits of nanophotonic design for precise and reliable ion manipulation.
Trapped-ion quantum computing requires precise optical control for individual qubit manipulation. However, conventional free-space optics face challenges in alignment stability and scalability as the number of qubits increases. Integrated photonics offers a promising alternative, providing miniaturized optical systems on a chip. Here, we propose a design for a multimode photonic circuit integrated with a surface-electrode ion trap capable of targeted and reconfigurable light delivery. Three closely positioned ions can be addressed using a focusing grating coupler that emits multimode light through electrode openings to ions trapped 68 μm above the chip. Simulations show that the couplers achieve a diffraction-limited spot with a 4.3 μm beam waist along the trap axis and 2.2 μm perpendicular to the trap axis. Controlled interference of the TE 00 and TE 10 modes results in crosstalk of –20 dB to –30 dB at ion separations of 5–8 μm when addressing ions individually, and down to –60 dB when two of the three ions are addressed simultaneously. Additionally, the higher-order TE modes can offer a novel mechanism for driving spin-motion coupling transitions, potentially enabling alternative approaches to quantum gates and simulations. The proposed integrated platform offers a viable path for constructing large-scale trapped-ion systems, leveraging the benefits of nanophotonic design for precise and reliable ion manipulation.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
Trapped ions are one of the most advanced platforms for quantum technologies, with applications ranging from quantum computing to precision timekeeping. A crucial step towards more compact and scalable systems involves integrating photonic integrated circuits (PICs) into surface ion traps to enable on-chip light delivery and optical addressing of individual ions. Currently, most implementations rely solely on transverse-electric (TE) mode grating couplers, where the emitted light is polarized in the plane of the chip. In this work, we design, fabricate and characterize key silicon nitride (Si3N4) PIC components required for scaling trapped-ion based quantum systems to multiple operating zones, including incoupling structures, splitters, and grating couplers that support both TE and transverse-magnetic (TM) modes with comparable optical losses. We benchmark the PIC at 760 nm, which is a typical wavelength for Yb+-applications. The fabricated grating couplers enable the outcoupling of collimated free-space beams for both polarizations, exhibiting distinct emission angles. This dual-polarization capability gives more flexibility in polarization control and expands the accessible optical design space for trapped-ion quantum technologies.